Etch Back Research Articles

Thermopile Infrared Detector with Detectivity Greater Than 108 cmHz(1/2)/W

In this paper, the design, fabrication and experimental results of the thermopile infrared detector, with a single layer of low-stress SiNx membrane, instead of thin sandwich layer membrane of SiO2–Si3N4 are presented. Thermal isolation is achieved by using back etching of bulk silicon. Thermopiles are consisted of serially interconnected p-poly-Si/Al thermocouples supported by the single layer of SiNx membrane with low stress. Au/Ti reflective coating was evaporated on the surface of cold junctions of the thermopile to block incident radiation. In the measurement, we find that infrared absorbance of SiNx membrane to different wavelength is diverse and less than 100%, which has great influence on calculating the actual absorbing power of the detector, so the infrared (IR) transmission spectrum is measured to calibrate the actual infrared absorbing amount of the detector. The analysis result shows that only 43.72% infrared radiation is absorbed by the detector. Based on the measurement of IR transmission spectrum and output voltage of the detector, the response sensitivity of the detector is calculated as 31.65 V/W, detectivity of the detector is 1.16 × 108 cmHz(1/2)W−1, and response time of the detector is 126 ms.

Effect of Residual Gradient Stress of Cantilever Plate Structure Deposited Metal Layers with Different Constraints on Deformation

Cantilever plate structure deposited metal layer is widely used MEMS. Due to mismatch of thermal expansion coefficients between structure and metal layers, residual gradient stress would be induced and deform structure as devices cooling down from process high temperature to room temperature. In this work, constraints effect is investigated. There are three constraints discussed and could be fabricated by back etching, isotropic wet etching, and anisotropic dry etching. For detail analysis, finite element method is used to analyze. Different width and length of structure sizes are used to discuss constraint effect. From the results, it is found different constraint would affect deformation. Under the same structure sizes, flat surface constraint has the largest deformation. And ICP etching constraint has the smallest deformation. Due to mechanics behavior of plate being much different comparing to beam, deformation of plate is no long parabolic shape in length direction. There are complex deformations in width direction. It is also found the deformation is determined by mechanics behavior on constraints. Width and constraint types have no significant on deformation when length is large at free end and middle section. And length has no significant effect on deformation for ICP and backside etching at clamped end. Temperature would induce increasing deformation linearly at free end and middle section.

Investigation of a Sequential Three-Dimensional Process for Back-Illuminated CMOS Image Sensors With Miniaturized Pixels

A new 3-D CMOS image sensor architecture is presented as a potential candidate for submicrometer pixels. To overcome the scaling challenge related to miniaturized pixel design rules, far beyond traditional 3-D stacking alignment capabilities, a sequential construction is applied. This paper gives a technical overview of this 3-D scheme and validates a part of its building blocks. As a consequence of a sequential process, the thermal budget is limited to ensure bottom device immunity. Subsequently, high-quality SOI film transfer above the first layer by direct bonding and etch back is demonstrated. Finally, the low-temperature processing of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TiN fully depleted silicon-on-insulator readout transistors is detailed and evaluated from a low frequency noise point of view.

Multilevel Interconnect With Air-Gap Structure for Next-Generation Interconnections

A misalignment-free multilevel air-gap interconnect with a via-base structure was fabricated by self-aligned gap formation and etch back. Its reliability was investigated by measuring stress-induced voiding, electromigration (EM), and time-dependent dielectric breakdown (TDDB). There was no via degradation after thermal stress (at 200degC for 500 h). The EM lifetime was the same as that of a conventional damascene interconnect, and the TDDB lifetime was about two orders of magnitude longer. Increasing the etch-back thickness of the interlayer dielectric increased the capacitance reduction by about 17%-32%. The frequency of a ring oscillator with an air-gap interconnect was higher by 17% on average than that with a conventional damascene interconnect. The simulation results demonstrate that this air-gap interconnect has the effective dielectric constant required for next-generation interconnects (22-nm node).

Fatigue failure characteristics of lead zirconate titanate piezoelectric ceramics

Mechanical properties and fatigue failure characteristics of lead zirconate titanate piezoelectric ceramic (PZT) have been investigated. Bending and fatigue strengths of PZT ceramic are directly attributed to the electrode status. Material hardening occurs in the PZT ceramic during the cyclic loading, which is influenced by domain switching occurring anywhere in the grains. The domain structure is clearly detected by electron back scatter diffraction analysis and etching techniques. It also appears that the poling direction causes the change of failure characteristics due to different domain and domain wall orientation. The domain orientation changes alternately from domain to domain by 90°. Moreover, the domain wall orientation is well regulated in the grains perpendicular to the poling direction. An acceleration of fatigue crack growth occurs as the crack propagates along the domain wall.

A novel technique of fabricating rear 45° micromirror for stacked die optical interconnect

This paper presents a novel technique of fabricating rear 45° micromirror which is located on the upper die to direct a vertical optical beam from the bottom die to propagate horizontally in the upper die. The fabrication of the 45° micromirror is based on anisotropic wet etching on (100) crystalline silicon surface. By using surfactant NCW-1002 in low concentration TMAH (2.5% to 10%) smooth (110) 45° micromirrors can be fabricated. Together with a suitable orientation of the back side etch window, this 45° micromirror provides the framework for fabricating the rear 45° micromirror.

Microstructuring of 45-µm-Deep Dual Damascene Openings in SU-8/Si by UV-Assisted Thermal Imprinting with Opaque Mold

In this study, we demonstrated a process for fabricating a dual damascene opening in a chemically amplified negative UV photoresist, such as SU-8. The process is based on a UV-assisted thermal-imprinting process, which involved UV pretreatment and thermal imprinting using a Ni mold. After establishing process parameters (e.g., adhesion enhancing, UV pre-treating, thermal imprinting, and etch back conditions) for the given geometry and dimensions of the mold pattern, we could successfully form 25-µm-deep trenches with a 10 µm line-and-space pattern and 45 µm-deep via holes in SU-8/Si samples by UV-assisted thermal imprinting, followed by O2/CHF3 reactive ion etching (RIE). Delamination defects could be avoided with the help of adhesion enhancement treatment. The process studied here showed great potential in reducing time and cost compared with the standard photolithographic dual damascene process.

High-aspect-ratio through-wafer parylene beams for stretchable silicon electronics

A low-temperature (<400 °C), CMOS compatible, post-processing module for converting a rigid silicon wafer into a stretchable electronic system is presented. The fabrication sequence is based on a combined use of narrow and wider through-wafer trenches forming a silicon mold for conformal parylene deposition. As only the narrow trenches are fully filled with parylene, two subsequent back plasma etching steps are used to remove first the parylene in the wider trenches and then also selected parts of the exposed silicon mold. This sequence results in an array of arbitrary-sized silicon segments containing active electronics/transducers interconnected with plurality of flexible high-aspect-ratio parylene beams (width of 20–30 μm; height equal to the wafer thickness, i.e. >200 μm) using one masking step only. The proposed post-processing module was successfully demonstrated on a 4 by 4 array of dummy silicon segments and a wafer thickness of 260 μm. Next to the stretchable mechanical interconnection, the proposed module allows also embedding of aluminum electrical interconnect lines within the parylene beams thus potentially realizing a fully functional stretchable system.

Simulation of Anisotropic Etching of Silicon using a Cellular Automata Model

In this work we present a 3D simulation software for anisotropic etching of crystalline silicon substrates in KOH solutions. The software is based on conventional cellular automata model, and integrates in the same environment, the simulator itself with different 2D and 3D graphics tools to define simulation parameters and for visualization purposes. The software simulates the etching of (100) oriented Si substrates through open regions in a masking material with arbitrary geometry, with any number of holes and island in the masking material, which can be isolated or one inside the others. The simulator also works with both, front and back side etching of the substrate at the same time. The results show that, even though the model is based on fixed and simple transitions rules to determine if a specific atom is removed or not by the etching process, the simulation results exhibit a quite good accordance with the experimental results.

Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. N-MOS devices thus fabricated with gate length ~150 nm showed excellent transistor characteristics with large drive current (1.0 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> muA/mum), high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ), good subthreshold slope (~80 mV/dec) and low drain-induced barrier lowering (~10 mV/V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.

A 1-D Photonic Band Gap Tunable Optical Filter in (110) Silicon

In this paper, we describe an electrostatically tunable optical bandpass filter that is fabricated in (110) silicon. Deep reactive-ion etching is the main process that is used to fabricate the overall device structure. To create the highly parallel surfaces that are needed for the photonic band gap elements, electrochemical (KOH) etching of the vertical (111) planes is then used. Back etching is used to release the moving parts. Fiber pigtails are attached in etched alignment grooves, and fiber-fiber insertion loss below 11 dB was obtained. The measured passband width was 3 nm with a tuning range of 8 nm.

Template replication for full wafer imprint lithography

Typically, the Step and Flash Imprint Lithography (S-FIL TM) process uses field-to-field drop dispensing of UV-curable liquids for step-and-repeat patterning. Several applications, including patterned magnetic media, photonic crystals, and wire grid polarizers, are better served by a process that allows high-throughput, full-wafer patterning of sub-100 nm structures with modest alignment. Full-wafer imprinting requires a full-wafer template; however, creation of a wafer-scale imprint template with sub-100 nm structures is not feasible with direct-writing approaches. This paper describes a practical methodology for creating wafer-scale templates suitable for full-wafer imprinting of sub-100 nm structures. The wafer-scale template is replicated from a smaller area master template using the S-FIL step-and-repeat process. The pattern is repeated to accommodate the wafer substrate targeted for a particular application. The tone of the master template is maintained by employing an SFIL/R TM (reverse tone) pattern transfer process. To create the replicate template, the patterns are imprinted onto a fused silica wafer that has been coated with chromium and an organic transfer layer. A silicon-containing resist, Silspin TM, is spun on to planarize the organic monomer material. Following an etch back of the Silspin, the monomer and transfer layer are patterned using the Silspin as a hard mask. The Silspin and monomer stack then serves as a masking layer for the chromium and fused silica etches. The remaining monomer and chromium are then removed to create a conformal replicate template.

Highly Arsenic Doped CdTe Layers for the Back Contacts of CdTe Solar Cells

AbstractIn an effort to overcome the lack of a suitable metal as an ohmic back contact for CdTe solar cells, a study was carried out on the potential for using a highly arsenic (As) doped CdTe layer with metallization. The deposition of full CdTe/CdS devices, including the highly doped CdTe:As and the CdCl2 treatment, were carried out by metal organic chemical vapour deposition (MOCVD), in an all-in-one process with no etching being necessary. They were characterized and compared to control devices prepared using conventional bromine-methanol back contact etching. SIMS and C-V profiling results indicated that arsenic concentrations of up to 1.5 × 1019 at·cm-3 were incorporated in the CdTe. Current-voltage (J-V) characteristics showed strong improvements, particularly in the open-circuit voltage (Voc) and series resistance (Rs): With a 250 nm thick doped layer, the series resistance was reduced from 9.8 Ω·cm2 to 1.6 Ω·cm2 for a contact area of 0.25 cm2; the J-V curves displayed no rollover, while the Voc increased by up to 70 mV (~ 12 % rise). Preliminary XRD data show that there may be an As2Te3 layer at the CdTe surface which could be contributing to the low barrier height of this contact.

InGaN Layers Grown on Al2O3/ZnO Substrates Prepared by Atomic Layer Deposition

AbstractAtomic layer deposition (ALD) of Al2O3 is used as a passivation layer on ZnO substrates before nitride growth by metalorganic chemical vapor deposition (MOCVD). This layer is being used to prevent Zn diffusion from the substrate, protect the ZnO surface from H2 back etching, and promote high quality nitride growth. ALD-Al2O3 films were grown at 100°C and then annealed in a furnace at various times at 1100°C for crystallization of the passivation layer. XRD results showed both Al2O3 and ZnAl2O4 phases at different intensities for 50 and 20nm ALD-AlM2O3 films. In addition, the InGaN layer has been successfully grown on the passivated ZnO substrate. Findings show that a short annealing time for the ALD-Al2O3 layer will be optimal for InGaN growth.

Nanoscopically Flat Open-Ended Single-Walled Carbon Nanotube Substrates for Continued Growth

Continued growth is a way of growing nanotubes targeted to produce continuous and chirality-controlled single-walled carbon nanotube (SWNT) materials. This growth method strongly depends on efficient preparation of open-ended SWNT substrates. Nanoscopically flat open-ended SWNT substrates have been prepared by cutting the SWNT spun fiber with a focused ion beam cutting technique and followed by etching schemes for cleaning amorphous carbon and opening the ends of the SWNTs. The open ends were effectively characterized through selective etch back of open SWNT ends by carbon dioxide gas at 950 degrees C. High density continued growth was demonstrated from these nanoscopically flat open-ended substrates.

Study of plasma charging-induced white pixel defect increase in CMOS active pixel sensor

Plasma process-induced “white pixel defect” (WPD) of CMOS active pixel sensor (APS) is studied for Si3N4 spacer etch back process by using a magnetically enhanced reactive ion etching (MERIE) system. WPD preferably takes place at the wafer edge region when the magnetized plasma is applied to Si3N4 etch. Plasma charging analysis reveals that the plasma charge-up characteristic is well matching the edge-intensive WPD generation, rather than the UV radiation. Plasma charging on APS transfer gate might lead to a gate leakage, which could play a role in generation of signal noise or WPD. In this article the WPD generation mechanism will be discussed from plasma charging point of view.

Single carbon fiber as a sensing element in pressure sensors

The principal and innovative concept of this research is the replacement of piezoresistors in the current piezoresistive pressure sensors with carbon fibers. The piezoresistive characteristics of carbon fibers can play the same role as piezoresistors in current pressure sensors. The main structure of pressure sensors was built by back side etching on a silicon-on-insulator wafer to create a square diaphragm. Dielectrophoresis was used for the alignment and deposition of carbon fiber across the gap between two electrodes. The fabricated pressure sensors clearly showed linear response to applied pressure, so the feasibility of carbon-fiber-based pressure sensors was demonstrated.

Wafer Bonding of CdZnTe / Si Structures

In this work, we demonstrate the transfer of Cd0.96Zn0.04Te layers to Si substrates by both bond and etch back and by ion exfoliation techniques. The (211)A face was employed for the bonding face to expose the pre-ferred (211)B face for subsequent HgCdTe growth. SiN intermediate lay-ers were used to facilitate the bond process. For the bond-and-etch proc-ess, 10 mm CdZnTe layers were transferred to silicon substrates. For ion-exfoliated layers, layers of 0.3 - 1 μm were transferred. The low level of implant-induced strain in the rpe-exfoliated layer is consistent with results from other materials. After transfer, these structures exhibited no strain and exhibited high crystal quality (as determined by double crystal x-ray topography and triple axis x-ray diffraction).

Evaluation of air gap structures produced by wet etch of sacrificial dielectrics: Extraction of keff for different technology nodes and film permittivity

Air gaps are a promising alternative to porous low- k dielectrics to achieve ultra low k-values in Cu damascene interconnects. Two approaches of air gap formation using wet etch back of sacrificial PECVD SiO 2 dielectrics were evaluated concerning their achievable effective k-values. Finite element method (FEM) simulations were performed to extract the effective k-value for different technology nodes. General k eff extraction procedure by FEM simulation is described. Furthermore the impact of variation of thickness and k-value of the functional layers applied for air gap formation was investigated. These functional layers are etch stop, cap and mask layers and currently consist of PECVD SiC: H films. It has been shown, that both parameters (thickness and k-value) considerably contribute to the effective k-value. For both investigated technology nodes, the 65 and 45 nm node, parameters can be found to fulfill the ITRS requirements [International Technology Roadmap for Semiconducors, 2000–2004, Semiconductor Industry Association, San Jose, CA, 2005.] for k eff. Lower k-values of the functional layers are needed, if the thickness has to be increased for processing reasons. For example k = 5.5 and thickness of 15 nm yield a k eff of about 2.5 for the 45 nm node. Ultimate effective k-values of 2.0 and below could be achieved for lower k-value or thickness of the functional films.

Film thickness and chemical processing effects on the stability of cadmium telluride solar cells

The performance and stability of CdS/CdTe solar cells as a function of layer thickness, back contact etch, and oxygen during the CdCl2 anneal was determined. Multiple linear regression models were used to analyze the statistical significance of various first order effects and interactions. With stress, all devices showed a reduction in open-circuit voltage (Voc) and fill factor (FF) characteristic of increased recombination. Devices using thinner CdS were vulnerable to shunt formation. Oxygen during the CdCl2 anneal minimizes this effect. A thermodynamic model involving the formation of Cu-oxide is presented to explain the latter.