High-aspect-ratio through-wafer parylene beams for stretchable silicon electronics

Abstract

A low-temperature (<400 °C), CMOS compatible, post-processing module for converting a rigid silicon wafer into a stretchable electronic system is presented. The fabrication sequence is based on a combined use of narrow and wider through-wafer trenches forming a silicon mold for conformal parylene deposition. As only the narrow trenches are fully filled with parylene, two subsequent back plasma etching steps are used to remove first the parylene in the wider trenches and then also selected parts of the exposed silicon mold. This sequence results in an array of arbitrary-sized silicon segments containing active electronics/transducers interconnected with plurality of flexible high-aspect-ratio parylene beams (width of 20–30 μm; height equal to the wafer thickness, i.e. >200 μm) using one masking step only. The proposed post-processing module was successfully demonstrated on a 4 by 4 array of dummy silicon segments and a wafer thickness of 260 μm. Next to the stretchable mechanical interconnection, the proposed module allows also embedding of aluminum electrical interconnect lines within the parylene beams thus potentially realizing a fully functional stretchable system.