ESD Protection Network Research Articles

New measurement method to investigated service life of protection networks exposed to ESD

This paper presents a new measurement method that enables investigating the degradations of protection networks under cumulative ESD pulses. The setup is based on a transmission line pulse (TLP) combined with time domain reflectometry (TDR) to get access to the complex impedance of the device under test. One of the advantages of the technique is that the frequency behaviour of the DUT is extracted as the same time the device is aged. The method is validated on a stable component and different devices are tested. Results show that after a certain number of pulses, the characteristic of the device have changed significantly. The extracted impedances can then be used into system design flow to investigate the impact of ESD stresses on sustainability of ESD protection network. Observations on the deviations of these input protection networks could also have impact on the electromagnetic immunity networks.

Note: Development of sTGC strip front-end readout prototype for ATLAS new small wheel upgrade.

This note presents the development of front-end electronics prototype for A Toroidal LHC ApparatuS (ATLAS) New Small Wheel (NSW) detector small-strip Thin Gap Chamber (sTGC) to be used for level-1 triggering and precision muon tracking at the Large Hadron Collider. The sTGC front-end electronics must deal with a large number of strip channels with very limited space constraint, large dynamic range of charge readout with low noise, simultaneous fast trigger, and precision readout data movement. The prototype uses custom radiation-tolerant application specific integrated circuits, optimized layout, power, and ESD protection networks to realize the above stringent requirements. The electronic test indicates that the front-end channel has a dynamic range of 900 pC and inherent noise of 0.19 fC. The sTGC cosmic ray test verified the precision charge measurement of the prototype, reconstructed the muon track, and measured the performance of sTGC. The NSW trigger chain test verified the trigger processing and 4.8 Gbps transmission of the prototype.

Thin-Copper-Metal Interconnection Thermomigration Analysis in ESD Regime

Technological scaling poses severe constraints on the design of metal interconnections, particularly for ESD protection network routing in advanced smart-power technologies. A detailed analysis of thin-interconnection failure mechanisms under high power pulses and their related root causes is mandatory. In this paper, this analysis is illustrated using characterizations, failure analyses, and 3-D TCAD physical simulations data.

Influence of Package Trace Properties on CDM Stress

CDM current waveform properties show a strong dependence on pin type and location due to package transmission line effects in large BGAs. I/O pin waveforms have a depressed peak, slower rise time, and increased pulsewidth compared to power supply waveforms, with the offset increasing with the distance from the package center. Simulations illustrate that the internal current through the ESD protection network on the die can deviate significantly from the external current observed in the CDM system for long package traces.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

Cross-Coupling Low-Triggering Dual-Polarity CLTdSCR ESD Protection in CMOS

This letter reports a novel ultrafast cross-coupling low-triggering dual-polarity SCR (CLTdSCR) ESD protection network in a CMOS. The measurement shows ultralow and tunable triggering voltage Vt1 ~ 3.83 V, low discharging resistance Rοn 0.26 Ω, low leakage Ileak ~ 0.36 nA, low noise figure NF ~ 0.2 dB, low parasitic capacitance CESD ~ 150 fF, and fast effective response t1 ~ 100 ps. It achieves a very high ~7 V/μm2 ESD protection level.

Comprehensive ESD protection approach in advanced CMOS SOI technologies

In this paper we describe a 90 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. We compare TLP results of SOI MOSFETs and diodes to bulk devices. We present a new response surface method to optimize device sizes in the ESD networks and show circuit level data comparing TLP test results and SPICE simulation results of an I/O test circuit. We also present product test data for standard ESD stress models.

ESD protection for broadband ICs (DC–20 GHz and beyond)

A proposal to design on-chip ESD protection networks as part of broadband microwave filters is presented. Simulation results show the viability of this approach in the presence of circuit parameter variations and non-ideal quality factors of on-chip elements. Illustrative examples are given for cutoff frequencies up to 20 GHz and beyond.

Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

This paper introduces a new distributed active MOSFET rail clamp network that offers surprising advantages in layout area efficiency, bus resistance tolerance, design modularity, and ease of reuse. SPICE simulation results using an extended vertical PNP bipolar transistor compact model and a new method for optimizing distributed rail clamp networks are presented along with chip-level test results.

ESD robustness prediction and protection device design in partially depleted SOI technology

In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD–SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width ( I t2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM–ESD) stress pulses. Furthermore, I t2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM–ESD protection levels of ±3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170–71).

ESD protection in thin film silicon on insulator technologies

This paper reviews some of the devices and circuits which have been used to implement ESD protection networks for thin film silicon on insulator (TFSOI) technologies. The high current behavior of TFSOI MOSFETS and diodes is described for both positive and negative discharges. Next, several representative pin-protection network designs are reviewed which have all been shown to provide industry-standard levels of ESD protection. A discussion of power-supply protection networks follows, which must be used in conjunction with the pin protection schemes.

CMOS-on-SOI ESD protection networks

ESD robustness of 4 kV HBM is achieved in CMOS-on-SOI ESD protection networks in an advanced sub-0.25 μm mainstream CMOS-on-SOI technology. Design layout, body contact, floating-gate effects and novel ESD protection implementations are discussed.

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, and ESD test data, will be shown for shallow trench isolation (STI) and LOCOS CMOS technologies.

A method for the characterization and evaluation of ESD protection structures and networks

The real-time measurement of current and voltage waveforms and the Emission Microscopy analysis, both performed during periodic non-destructive simulated ESD events on ESD protection devices, allows (i) the study of the dynamic electrical behaviour and the ESD current distribution of single protection structure and (ii) the localization of the ESD current path along a complex protection network. These two techniques, in addition to the traditional ESD step stress test, can be used to evaluate both the hardness and the effectiveness of ESD protection devices.

A newly observed high frequency effect on the ESD protection utilized in a gigahertz NMOS technology

The standard ESD protection network incorporated onto NMOS integrated circuits is found to turn on partially when subject to valid low voltage waveforms in high frequency applications. We report on a study of this phenomenon, and present a physical model that explains our observations. It is suggested that the underlying mechanism contributes to the excellent defense provided by the protection circuitry in conventional usage against damage from large voltage, fast transients.

Analysis of ESD protection networks for DMOS power transistors by means of static and time‐resolved emission microscopy

AbstractDifferent ESD input/output protection networks, based on Zener diodes and lateral npn transistors have been implemented with the aim of characterizing their effectiveness in protecting vertical DMOS power transistors. Failure mechanisms have been identified by means of static emission microscopy. Gated emission microscopy, in synchronism with a voltage pulse emulating the ESD event, enables the dynamic behaviour of protection structures to be analysed, identifying lateral current crowding effects which explain the observed failure mechanisms.