ESD Protection Design Research Articles

A Dual-directional SCR based ESD Protection Design with High Holding Voltage using Embedded MOSFET for 12-V Applications

A Dual-directional SCR based ESD Protection Design with High Holding Voltage using Embedded MOSFET for 12-V Applications

Analysis of the behavior of TCAD and SPICE diode models in ESD protection circuits

To protect the interfaces of high-speed ICs from ESD, it is necessary to develop and optimize specialized protection circuit designs to minimize parasitic capacitance. The classic widely used designs based on ggMOS and SCR have too large parasitic capacitance, which degrades the parameters of the interface pins of the ICs. It is necessary to develop and optimize other ESD protection designs. One of the possible promising options is optimized diode protection. In this paper, an analysis of the effect of the design of a diode protection on its electrical characteristics is carried out. An analysis of the possibility of modeling protection using SPICE models was also performed and an assessment of the need to use TCAD simulation was carried out. Based on a comparison of the results of SPICE and TCAD simulations, it is shown that widely used SPICE diode models not optimal for designing and optimizing diode ESD protection. For this task, it is necessary to use TCAD simulation, taking into account the self-heating of the structure and the dynamics of the propagation of the thermal front. The results of this work are used for the development of ESD protection for interfaces of high–speed microcontrollers, DACs/ADCs, and transceivers.

Investigation on holding voltage of asymmetric DDSCR with floating heavy doping in 0.18 μm CMOS process

In the ESD protection design work, the most effective way to improve the holding voltage of bidirectional silicon-controlled rectifier or SCR device is to increase the distance between the cathode and anode of it. However, for DDSCR devices with multi-finger layouts, increasing this distance will result in a decrease in failure current and require a larger layout area. In this work, five types of asymmetric dual direction silicon-controlled rectifier devices with different floating heavy doping combinations are designed based on the traditional ADDSCR structure. Meanwhile, the dimensions, number of fingers, metal layout and number of CONT holes of the five ADDSCR structures are strictly kept the same, aiming at studying the influence of different floating heavy doping combinations on the performance of SCR devices and find the optimal floating heavy doping combination. Their ESD performances are predicted and verified through the two-dimensional device simulations and transmission line pulse (TLP) test results. All the five types of ADDSCR structures are designed to improve the holding voltage. From the results, the forward and reverse holding voltage of ADDSCR_PP, which is inserted floating P+ in NW and PW, are increased to 20.4 V and 17.6 V respectively, compared with the traditional devices without floating heavy doping at 14.2 V and 8.7 V. At the same time, the physical mechanism for the effect of floating heavy doping insert into NW and PW separately were investigated. Finally, the one that best meets the ESD window of automotive application is found.

Design of an On-Board ESD Protection for USB3 Applications

This paper describes the development of an on-board system level protection for high-speed cable connections (e.g., USB3) with 15 kV robustness and a signal transfer rate of up to 10 Gb/s. A dedicated bipolar process is developed, on a high-resistive substrate with optimized diffusion profiles and a special via-on-via metallization to meet the capacitance target of 0.25 pF. The protection is shown to work well with several popular USB3 chipsets.

EMMI Failure-Distributed Analysis of ESD Zapping and Protection Designs in Power VDMOS ICs

This paper deals with a detailed study of ESD failure modes, failures distribution and how to strengthen of the VDMOS ICs used for power applications. The ESD post-zapped failure of power VDMOS ICs due to HBM, MM, and CDM stresses are examined in this work. Through standard failure analysis techniques by using EMMI and SEM were applied to identify the failure locations. It is found that the ESD robustness is VESD(HBM) > VESD(MM) > VESD(CDM) for these non-ESD protected DUTs. Meanwhile, the ESD failure sites will be closed to the gate bonding pad as with a positive zapping and higher dV/dt pulse such as in CDM testing. And, the failure mappings have been studied to establish the difference in damaged features of HBM, MM, and CDM. Furthermore, the ESD protection designs of power VDMOS ICs are also addressed in this work. The first ESD incorporated design is Zener diodes back-to-back clamping the gate-to-source pad, and on the other hand, another one excellent design contains two Zener diodes clamping the gate-to-source and gate-to-drain terminals of a VDMOS, respectively.

Dual-Direction Nanocrossbar Array ESD Protection Structures

This letter reports a new nanocrossbar array ESD protection design. The unique nanocrossbar array structures ensure uniform ESD discharging and achieve fast ESD response speed and >; 8A ESD protection capability in prototypes. The nanoswitching ESD protection effect eliminates large leakage current inherent to traditional p-n-junction-type ESD protection devices.

Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs

For integrated circuits (ICs) with voltage programming pin ( pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to cannot be applied to such pin. In this work, a new ESD protection design is proposed to improve ESD robustness of pin with the consideration of the mistriggering issue when programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.

On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs

An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100ns TLP system. From the HBM/CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1kV, MM 100V and CDM 500V.

Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits

SUMMARY An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-μm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be codesigned with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.

The design of high holding voltage SCR for whole-chip ESD protection

In this paper, we have investigated the electrical characteristics of Silicon Controlled Rectifier (SCR)-based ESD power clamp circuit with high holding voltage for whole-chip ESD protection. The proposed ESD power clamp circuit (HHVSCR: High Holding Voltage SCR) has different well (n/p-well) length (3/7µm - 8/2µm) and p-drift (p+) length (8µm - 16µm). The measurement results indicate that dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V) and a little effect on the triggering voltage (6.5V∼7V). And the whole-chip ESD protection was designed for 2.5∼3.3V applications, this whole-chip ESD protection design can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. The robustness of the novel ESD protection cells were measured to 6kV (HBM: Human Body Model), 280V (MM: Machine Model).

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness.

Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology

In order to enhance the applications of SCR devices for deep-submicron CMOS technology, a novel SCR design with function is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device (NMOS with almost zero or even negative threshold voltage) or any process modification, this initial-on SCR design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design has a high enough holding voltage to avoid latchup issues in a VDD operation voltage of 2.5 V. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a fully-silicided 0.25-mum CMOS process

SCR-based ESD protection in nanometer SOI technologies

This paper introduces an SCR-based ESD protection design for silicon-on-insulator (SOI) technologies. SCR devices or thyristors, as they are sometimes better known, have long since been used in Bulk CMOS to provide very area efficient, high performance ESD protection for a wide variety of circuit applications. The special physical properties and design of an SOI technology however, renders straightforward implementation of an SCR in such technologies impossible. This paper discusses these difficulties and presents an approach to construct efficient SCR devices in SOI. These devices outperform MOS-based ESD protection devices by about four times, attaining roughly the same performance as diodes. Experimental data from two 65 nm and one 130 nm SOI technologies is presented to support this.

Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices

A novel self-substrate-triggered technique for on-chip ESD protection design is proposed to solve the non-uniform turn-on phenomenon of multi-finger gate-grounded nMOS (GGnMOS). The center-finger nMOS transistors in the multi-finger GGnMOS structure are always turned on first under ESD stress, so its source terminal is connected to the base (substrate) terminals of the other parasitic lateral n-p-n bipolar transistors (BJTs in the GGnMOS structure) to form the self-substrate-triggered design. With the proposed self-substrate-triggered technique, the first turned-on center-finger nMOS transistors are used to trigger on the others. Therefore, all fingers of GGnMOS can be triggered on simultaneously to discharge ESD current. From the experimental results verified in a 0.13-mum CMOS process with the thin gate oxide of 25 Aring, the turn-on uniformity and ESD robustness of the GGnMOS can be greatly improved without increasing extra layout area through the proposed self-substrate-triggered technique

Comprehensive ESD protection approach in advanced CMOS SOI technologies

In this paper we describe a 90 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. We compare TLP results of SOI MOSFETs and diodes to bulk devices. We present a new response surface method to optimize device sizes in the ESD networks and show circuit level data comparing TLP test results and SPICE simulation results of an I/O test circuit. We also present product test data for standard ESD stress models.

Implementation of plug-and-play ESD protection in 5.5 GHz 90 nm RF CMOS LNAs—Concepts, constraints and solutions

Design and implementation of ESD protection for a 5.5 GHz low noise amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as “plug-and-play”, is used as ESD protection for the RF pins. The consequences of design and process, as well as, the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail. Enhancement in the ESD robustness using additional core-clamp diodes is proposed.

Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design

The double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.

A new multi-finger SCR-based structure for efficient on-chip ESD protection

This paper introduces a new SCR-based (silicon controlled rectifier) structure for on-chip ESD protection. The STMSCR (smart triggered multi-finger SCR) relies on the bimodal operation of a LSCR (lateral SCR) using an external triggering circuitry that permits switching from a transparency mode to a protection mode as soon as an ESD event is detected. The trigger voltage can be adjusted by design without any impact on the ESD performance. The STMSCR is multi-finger compliant, thus allowing area-efficient design of pad-located ESD protection. The STMSCR is demonstrated in a 0.18 μm CMOS technology without any process customization; an HBM failure threshold over 115 V/μm is reached while always ensuring current uniformity in multi-finger structures.

Latchup-free esd protection design with complementary substrate-triggered scr devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.

Process influence on product CDM ESD performance

Effective ESD protection circuit design has become challenging due to rapid advances in process technology. This study was launched to address those concerns in deep sub-micron technologies and to look for a process windows that preserve CDM ESD robustness for a given ESD protection designs. Experimental results for 0.18 μm integrated CPU’s together with process window effects on CDM robustness are presented and discussed. The correlation between electrical characteristics and some of the common failure modes are described. It is shown that transistor off current lower than critical value can lead to degradation in time and an eventual secondary breakdown in a parasitic NPN transistor that results in unexpected CDM sensitivity.