ESD Current Research Articles

A low power fully differential RF receiver front-end for 2.4 GHz wireless sensor networks

In this paper, a novel merged LNA-mixer denoted as LNMA is proposed. The proposed LNMA consisting of a folded cascode LNA using improved derivative superposition technique and folded double-balanced subthreshold mixer using capacitor cross-coupled common-gate transconductor and it is integrated with on-chip LC voltage controlled oscillator (LC-VCO). In LNMA, a diode and power clamp based on-chip ESD protection circuit is used to tolerate ESD current of human-body-model specifications. To evaluate its performance, it is implemented in 0.18-µm MMRF CMOS process with 1-V supply, studied through post layout simulation and compared the results with other reported works. It achieves higher conversion gain of 27 dB, lower noise figure of 9.5 dB, lower input return loss (S11) of − 20 dB, higher third-order input intercept point (IIP3) of – 16 dBm and higher IIP2 of + 29.9 dBm compared to the works reported in the literature. The on-chip oscillator has the lower phase noise of – 114 dBc/Hz. The proposed LNMA and the LC-VCO achieves the power consumptions of 1.6 and 1.72 mW, respectively at 1-V power supply.

Soft-Failures Induced by System-Level ESD

Hundreds of static discharges were directed to a circuit board containing a custom test chip, and the resulting soft-failures were recorded. The large time-derivative of the ESD current is the primary cause of soft-failures in this system. Magnetic coupling between traces and bondwires produces glitches at IO pins; the magnitude of these glitches is increased by the bounce of the on-chip supply net relative to the on-board supply. Additionally, logic upsets due to substrate current collection are observed when the equipment-under-test is tethered, i.e., when it has a low impedance path to Earth-ground.

향상된 전기적 특성을 갖는 저면적 ESD 보호회로에 관한 연구

본 논문에서는 향상된 전기적 특성과 면적효율을 갖는 새로운 구조의 ESD 보호회로를 제안한다. 제안된 회로는 기존의 3-STACK LVTSCR과 비교하여 높은 홀딩전압과 낮은 트리거전압 특성, 향상된 Ron 저항 특성을 갖는다. 제안된 ESD 보호회로는 기존 보호회로 대비 35% 정도의 작은 면적, 35V의 트리거 전압과 8.5V의 홀딩전압을 갖는다. 또한 제안된 ESD 보호회로의 래치-업 면역특성을 향상시키기 위해 기생 바이폴라 트랜지스터들의 유효 베이스 길이를 설계변수로 설정하여 설계하였고 시놉시스사의 TCAD 시뮬레이션을 통하여 제안된 ESD 보호회로를 검증하고 전기적 분석을 실행하였다. This paper presents the ESD protection circuit with improved electrical characteristic and area efficiency. The proposed ESD protection circuit has higher holding voltage and lower trigger voltage characteristics than the 3-Stacking LVTSCR. In addition, it has only two stages and has improved Ron characteristics due to short discharge path of ESD current. We analyzed the electrical characteristics of the proposed ESD protection circuit by TCAD simulator. The proposed ESD protection circuit has a small area of about 35% compared with 3-Stacking LVTSCR, The proposed circuit is designed to have improved latch-up immunity by setting the effective base length of two NPN parasitic bipolar transistors as a variable.

Layout optimization of GGISCR structure for on-chip system level ESD protection applications

To improve the holding voltage, area efficiency and robustness, a comparative study on single finger, 4-finger and round shape layout of gate-grounded-nMOS incorporated SCR (GGISCR) devices are conducted. The devices were fabricated with a commercial 0.35μm HV-CMOS process without any additional mask or process modification. To have a fair comparison, we develop a new Figure-of-Merit (FOM) modeling for the performance evaluation of these devices. We found that the ring type device which has an It2 value of 18.9A is area efficient and has smaller effective capacitance. The different characteristics were explained with the different effective ESD currents in these layout structures.

Transient voltage suppressor based on diode-triggered low-voltage silicon controlled rectifier

Transient voltage suppressor (TVS) has been widely used for electronic system ESD protection. A good TVS is usually costive as it needs some special processes and with extra masking layers for fabrication. A novel TVS design based on the standard CMOS process will be much attractive. This work proposes a new TVS device using a CMOS compatible diode-triggered silicon controlled rectifier (DLVTSCR) as the core device. Due to the available of multiple trigger mechanisms and the dual current paths for bypassing the ESD current, the newly proposed device is able to sink an ESD current of over 10 A. In addition, the holding voltage is promoted up to 6.83 V and the trigger voltage is lowered down to 10.8 V which is well suit for most portable device applications.

래치-업 면역과 높은 감내 특성을 가지는 LIGBT 기반 ESD 보호회로에 대한 연구

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

Investigation of the trigger voltage walk-in effect in LDMOS for high-voltage ESD protection

The trigger voltage walk-in effect has been investigated by designing two different laterally diffused metal—oxide—semiconductor (LDMOS) transistors with an embedded silicon controlled rectifier (SCR). By inserting a P+ implant region along the outer and the inner boundary of the N+ region at the drain side of a conventional LDMOS transistor, we fabricate the LDMOS-SCR and the SCR-LDMOS devices with a different triggering order in a 0.5 μm bipolar-CMOS-DMOS process, respectively. First, we perform transmission line pulse (TLP) and DC-voltage degradation tests on the LDMOS-SCR. Results show that the trigger voltage walk-in effect can be attributed to the gate oxide trap generation and charge trapping. Then, we perform TLP tests on the SCR-LDMOS. Results indicate that the trigger voltage walk-in effect is remarkably reduced. In the SCR-LDMOS, the embedded SCR is triggered earlier than the LDMOS, and the ESD current is mainly discharged by the parasitic SCR structure. The electric potential between the drain and the gate decreases significantly after snapback, leading to decreased impact ionization rates and thus reduced trap generation and charge trapping. Finally, the above explanation of the different trigger voltage walk-in behavior in LDMOS-SCR and SCR-LDMOS devices is confirmed by TCAD simulation.

Characteristic study on an ESD suppressor by the FDTD method

The FDTD method was used to study the characteristics of an ESD suppressor filled with air, neon, argon, and helium. Obtained capacitance of the ESD suppressor filled with air was validated by measurement data and TDMM simulations. No large differences are found among the obtained capacitances for the ESD suppressor filled with air, neon, argon, and helium. But the ESD suppressor filled with air has a much higher trigger and clamping voltage than the ESD suppressor filled with neon, argon, or helium. The calculated capacitances are presented for different conditions. The ESD currents, charges, and electric fields are also presented. ► The FDTD method was used to study the characteristics of an ESD suppressor. ► Obtained capacitance of the suppressor was checked by measured and numerical data. ► Higher trigger and clamping voltages were found for the suppressor filled with air.

Performance improvement of an ESD suppressor by studying its characteristics

The finite-difference time-domain (FDTD) method was used to study the characteristics of an ESD suppressor. The obtained capacitance of the ESD suppressor filled with air was validated by measurement data and another numerical result obtained by time-domain moment method (TDMM). Under the same conditions, no large differences are found among the obtained capacitances for the ESD suppressor filled with air, neon, argon, and helium. But the ESD suppressor filled with air has a much higher trigger and clamping voltages than the ESD suppressor filled with neon, argon, or helium. Capacitance is found to decrease with the increase of the spark gap distance or the operating frequency. But the capacitance increases with increasing relative dielectric constant of the substrate or the overcoat. t is observed that ESD currents with a transient waveform reach a maximum value and decays sharply as the time increases under the condition of the spark gap distance of 5 μm. Outside the spark gap, the maximum electric field is below the breakdown strength, but the magnitude of the electric field radiated from ESD events is still very large when the distance from the ESD suppressor is less than 2 mm.

The Characteristics of ESD Protection Device Based on Static Induction Thyristors

A novel structure of ESD protection device based on the static induction thyristors (SITh) was in further investigation. Detailed analysis of the negative resistance characteristics of SITh was presented, especially its blocking and conducting states that satisfy the requirements in ESD events. The characteristics of SITh for ESD protection were obtained using the Time Domain Reflectometer (TDR) type of Transmission Line Pulse (TLP) testing system. The results illustrate that SITh for ESD protection has the following advantages: 1) It has a strong ESD stress handing capability (3.75 kV); 2) Its second breakdown current is large enough (2.5 A) to release great ESD current; 3) DC leakage current of SITh is very small (1 μA); 4) SITh can break through the limitations of transitional trigger voltages, whose trigger voltage is dynamically adjustable as well; 5) The ESD response time can be controlled through optimizing device structure of SITh.

Analysis of electrostatic discharge suppressors with ultra-low capacitance used for IC protection

The TDMM was successfully used to analyze the capacitance, the electric field, and the ESD current of an ESD suppressor. The obtained capacitance was also validated by measurement data. It is found that the maximum electric fields in the air gap between two discharge electrodes for the air gap width of 5–50 μm are much higher than the threshold electric field for air breakdown. A maximum ESD current of 4.7 mA was obtained during an ESD event, which may be sufficient to cause a malfunction in a high sensitivity integrated circuit.

Reliability impact due to high current, lattice and hot carriers temperatures on β(2×2) matrix ESD power devices for advanced CMOS technologies

The main purpose of this paper is to present the behavior of a β(2×2) matrix ESD power device with the effects of high ESD current, lattice and hot carriers temperatures. The beta matrix is a candidate for ESD device network for advanced CMOS technologies. This demonstrator is done in C45 & C32nm CMOS technologies. The high ESD current, lattice temperature and hot carriers temperature are study thanks to 3D TCAD simulations in ACS stimulus. Thus, it is possible to identify the potential weakness point and optimize the topology of this kind of power device. Moreover, the IV curves are measured in TLP condition to determine the ESD response.

Modeling of contact discharge between floating devices

The Giant-magnetoresistive (GMR) head suffers magnetic damage from ESD current on the order of 10 mA and thermal damage from ESD energy on the order of 0.5nJ. Contact discharge from an electrified object into a floating device was investigated as the peak current caused magnetic damage and as the energy-loss caused thermal damage. Experiments with discharges between various capacitors clarified that the discharge between 2pF-capacitors at 10V gave a peak current of 34mA and the discharge between 100pF-capacitors at 100V reached 1.5A. A 2D-plot of the peak current simulated by PSPICE indicated that the peak value arose at the order of pF and was approximately maximized at the same value of both capacitors. Theoretical energy-loss was estimated by the difference between the potential energies prior to and following the discharges. The energy-loss was 0.05nJ for 2pF-capacitors at 10V and increased in excess of 0.5nJ when both capacitors were grater than 20pF. The energy-loss reached 250nJ for 100pF-capacitors at 100V. 2D-plot of the energy-loss indicated a gradual increase as both capacitance-values increased. In order to decrease the risk of ESD failure, reducing the capacitance of the device was effective, because the transferred-charge and energy-loss were restricted.

Study on ESD/EMI Phenomena for Magnetic Reproducing Head

GMR heads, the most electrostatic discharge (ESD/EOS) sensitive device of all electric devices, are used for high density magnetic recording applications. A number of problems related to electrostatic discharge phenomena in GMR heads have been reported, including melting and diffusion caused by the Joule heating by ESD currents, pinning rotation and demagnetization resulting from high magnetic field strength, and dielectric breakdown induced by a high voltage. In recent years, there has been a growing concern about damaging GMR heads from Electro-Magnetic Interference (EMI). In this paper, we studied a relatively easy method for comprehending the basic characteristics of EMI using the instruments that are widely used in conventional ESD evaluation for GMR head manufacturing.

Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices

A novel self-substrate-triggered technique for on-chip ESD protection design is proposed to solve the non-uniform turn-on phenomenon of multi-finger gate-grounded nMOS (GGnMOS). The center-finger nMOS transistors in the multi-finger GGnMOS structure are always turned on first under ESD stress, so its source terminal is connected to the base (substrate) terminals of the other parasitic lateral n-p-n bipolar transistors (BJTs in the GGnMOS structure) to form the self-substrate-triggered design. With the proposed self-substrate-triggered technique, the first turned-on center-finger nMOS transistors are used to trigger on the others. Therefore, all fingers of GGnMOS can be triggered on simultaneously to discharge ESD current. From the experimental results verified in a 0.13-mum CMOS process with the thin gate oxide of 25 Aring, the turn-on uniformity and ESD robustness of the GGnMOS can be greatly improved without increasing extra layout area through the proposed self-substrate-triggered technique

Measurements of air discharges from insulating, electrostatic dissipative and conductive materials with different ESD probes

In this work, we have compared the performance of three different kinds of passive resistor-transmission line ESD probes: an unshielded ball probe, a shielded ball probe with the ESD current collected on a coaxial wire tip, and a needle-like probe. We have measured discharges from ESD sources having different surface resistivities including charged insulator surfaces, electrostatic dissipative materials and metal plates. In compliance with the results, there is no single probe type that is ideal for all kinds of situations—there are significant differences between the probe responses comprising sensitivity, charge transferred and peak ESD current. As expected, the initiation of air discharges was suppressed in accordance with increasing surface resistivity of the ESD source.

Time varying magnetic fields generated by human metal (ESD) electrostatic discharges

In this paper it is shown that the magnetic fields very close to an ESD can be predicted by modelling the radiating discharge current path as a sequence of electric dipoles. Time domain measurements of current and magnetic fields generated by human-metal electrostatic discharges are used for verification. An ESD current of 10 A peak and 10 ns rise time can create magnetic fields of the order of 200 μT at a distance of 10 mm from the discharge.

Three-dimensional transient simulation of magnetoresistive head temperature during an ESD event

Magnetoresistive (MR) heads for disc drives are susceptible to very low levels of ESD in the manufacturing and assembly process. The cost of failed heads and the ESD controls in the factories are high. One mode of failure is overheating of the MR sensor due to the ESD current. Knowledge of the head design parameters which affect the peak ESD temperature are desirable to guide the head design. The MR sensor temperature during an ESD event is modeled in three dimensions using finite elements. Results are given for the relative effect of ESD with a range of thermal and electrical properties, dimensions, and discharge time constants. The key parameters are the material properties of the sensor and insulator, the sensor height, and the insulator thickness. Lateral heat conduction reduces the temperature at the edges of the sensor.

ESD: waveform calculation, field and current of human and simulator ESD

Currents, current derivatives and transient fields of human ESDs are compared to currents and fields caused by commercial simulators. The results point at undefined but influential parameters of simulators and the standardized setup used. Suggestions for possible improvements of ESD test standards are given. A calculation method for the ESD current is provided. This method includes an arc model. Possible high peak current values ( > 10 A/kV) are validated by a simple physical model of the hand-metal piece geometry. By calculation it is shown under which circumstances human ESD currents come close to the standardized waveform of simulators.

Off-chip protection: Shunting of ESD current by metal fingers on integrated circuits and printed circuit boards

Abstract Equalization of electrical potential of integrated circuit (IC) pins and printed circuit boards as a concept to prevent ESD damage is investigated experimentally and theoretically. Long metal traces of little DC resistance for potential equalization are shown to act like an open circuit to fast CDM-type ESD pulses. Effective ESD protection can be achieved by sharing ESD stress with neighboring pins.