Error Resilience Research Articles

BCS-Based Encoding Schemes for Monoview and Multiview Visual Configurations in WVSN Data Gathering: A Survey

Wireless Visual Sensor Network (WVSN) has become a valuable tool in addressing the evolving needs of modern monitoring systems. Encoding in WVSNs is a multifaceted process that involves compressing visual data, optimizing energy consumption, ensuring error resilience, and adapting to various network and application requirements. The associated lightweight encoders and the demand for less storage space make block compressive sensing (BCS) techniques suitable for WVSN applications where energy, bandwidth, and storage resources are limited. Based on the number of visual perspectives or camera angles available within a network for data capture, there are two primary congurations: monoview and multiview. This paper provides a comprehensive survey of dierent BCS-based encoding schemes used for data-gathering in both monoview and multiview scenarios within WVSNs. A comparative study of these algorithms based on compression level, computational complexity, relative gain in encoder energy, and reconstruction quality is performed. A BCS-based joint encoding scheme for multiview conguration that ensures a relatively high compression level is also proposed in this paper.

Design of Energy Efficient Arithmetic VLSI Circuits

Advanced electronics have become an integral part of human lives, from Smartphones in our pockets to the modern vehicles on the road and to the satellites that orbit the earth. Power consumption has become a major constraint in these applications, often employing data- intensive digital signal processing systems and architectures. While enormous transistor density at the nanoscale has been increased in the Very Large-Scale Integration (VLSI) multicore era comparable to Moore's law, improving the performance of computing systems has become extremely difficult. Sustaining technological advancements for such energy-constrained devices has paved the way for new areas in research. “Approximate Computing (AC)” has become one of the most promising paradigms, a field that has gainedsignificant attention in the quest for energy efficiency in recent years. AC algorithms are numerically approximate rather than accurate. Inherent error resilience is the primary source of motivation behind AC. Recent research demonstrates that error resilience is pervasive in cyber search, deep learning, multimedia, recognition and data mining. Arithmetic units are the fundamental building blocks in most of the data dominated applications at the micro- architectural level of abstraction. AC is optimal for power and area efficient arithmetic circuits.

Analyzing Quantum Error Resilience for Quantum Communication in Guided and Unguided Media

AbstractThis research examines quantum key distribution and its applications in guided and unguided quantum communication. The importance of secure communication in the quantum era requires a thorough exploration of both guided and unguided quantum communication strategies. The research aims to address the challenges posed by guided channels, such as fiber optics, and unguided channels, such as free‐space quantum communication. This study addresses existing knowledge gaps in quantum error resilience management and signal processing techniques in unguided quantum communication. Advanced quantum gate analysis, environmental noise analysis, and quantum channel modeling techniques are employed. The research presents key findings on the impact of gate imperfections on quantum error resilience in guided media, the influence of noise‐induced errors in unguided media, and a unified metric for assessing various error sources in guided channels. Additionally, the study analyses stabilizer codes and surface codes for error mitigation through quantum error correction strategies. Simulation results provide a benchmark for theoretical predictions and guide the refinement of quantum communication protocols. In this context, machine learning‐based error prediction is introduced as a cutting‐edge approach to enhance the robustness of quantum communication systems.

Increasing quantum communication rates using hyperentangled photonic states

Quantum communication is based on the generation of quantum states and exploitation of quantum resources for communication protocols. Currently, photons are considered as the optimal carriers of information, because they enable long-distance transition with resilience to decoherence and they are relatively easy to create and detect. Entanglement is a fundamental resource for quantum communication and information processing, and it is of particular importance for quantum repeaters. Hyperentanglement, a state where parties are entangled with two or more degrees of freedom (DoFs) simultaneously, provides an important additional resource because it increases data rates and enhances error resilience. However, in photonics, the channel capacity, i.e., the ultimate throughput, is fundamentally limited when dealing with linear elements. We propose a technique for achieving higher transmission rates for quantum communication by using hyperentangled states, based on multiplexing multiple DoFs on a single photon, transmitting the photon, and eventually demultiplexing the DoFs to different photons at the destination, using Bell state measurements. Following our scheme, one can generate two entangled qubit pairs by sending only a single photon. The proposed transmission scheme lays the groundwork for novel quantum communication protocols with higher transmission rates and refined control over scalable quantum technologies.

VSD: A Novel Method for Video Segmentation and Storage in DNA Using RS Code

As data continue to grow in complexity and size, there is an imperative need for more efficient and robust storage solutions. DNA storage has emerged as a promising avenue to solve this problem, but existing approaches do not perform efficiently enough on video data, particularly for information density and time efficiency. This paper introduces VSD, a pioneering encoding method for video segmentation and storage in DNA, leveraging the Reed–Solomon (RS) error correction code. This method addresses these limitations through an innovative combination of segmentation and encoding, accompanied by RS coding to bolster error resilience. Additionally, the method ensures that the GC-content of the resultant DNA sequences remains around 50%, which further enhances the storage robustness. The experimental results demonstrate the method has commendable encoding efficiency and offers a solution to the prevailing issue of time inefficiency and error correction rates in DNA storage. This groundbreaking approach paves the way for the practical and reliable storage of large-scale video data in DNA, heralding a new era in the domain of information storage.

Training-Free Quantum Architecture Search

Variational quantum algorithm (VQA) derives advantages from its error resilience and high flexibility in quantum resource requirements, rendering it broadly applicable in the noisy intermediate-scale quantum era. As the performance of VQA highly relies on the structure of the parameterized quantum circuit, it is worthwhile to propose quantum architecture search (QAS) algorithms to automatically search for high-performance circuits. Nevertheless, existing QAS methods are time-consuming, requiring circuit training to assess circuit performance. This study pioneers training-free QAS by utilizing two training-free proxies to rank quantum circuits, in place of the expensive circuit training employed in conventional QAS. Taking into account the precision and computational overhead of the path-based and expressibility-based proxies, we devise a two-stage progressive training-free QAS (TF-QAS). Initially, directed acyclic graphs (DAGs) are employed for circuit representation, and a zero-cost proxy based on the number of paths in the DAG is designed to filter out a substantial portion of unpromising circuits. Subsequently, an expressibility-based proxy, finely reflecting circuit performance, is employed to identify high-performance circuits from the remaining candidates. These proxies evaluate circuit performance without circuit training, resulting in a remarkable reduction in computational cost compared to current training-based QAS methods. Simulations on three VQE tasks demonstrate that TF-QAS achieves a substantial enhancement of sampling efficiency ranging from 5 to 57 times compared to state-of-the-art QAS, while also being 6 to 17 times faster.

Comparative analysis of soft-error sensitivity in LU decomposition algorithms on diverse GPUs

Graphics processing units (GPUs) have become integral to embedded systems and supercomputing centres due to their large memory, cutting-edge technology and high performance per watt. However, their susceptibility to transient errors requires a comprehensive analysis of error sensitivity, as well as the development of error mitigation techniques and fault-tolerant algorithms. This study focuses on evaluating the soft-error sensitivity of two distinct versions of LU decomposition algorithms implemented on two very different GPUs—a low-power SoC embedded GPU and a high-performance massively parallel GPU. Through extensive fault injection campaigns on both GPUs, we examine the vulnerability of the algorithms, identify error causes, and determine critical code components requiring enhanced protection. The experiments reveal that most single bit flip fault injections in the instruction results lead to erroneous outcomes or unrecoverable errors. Notably, efficient GPU resource utilisation can increase the number of masked errors, thereby enhancing error resilience. Additionally, while different parts of the code exhibit similar error occurrence types and rates, the propagation of errors to elements within the result matrix differs significantly.

DUAL-C: Building a “soft error efficient” on-the-fly compression mechanism for raw video data at edge devices

Nowadays, various edge applications play an increasingly important role in our life, in which video data accounts for a dominant portion of the data traffic. Although standard compression methods, such as H.264 and MPEG4, can considerably reduce the wireless bandwidth for transmission energy savings of edge devices, the large volume of raw video streaming data is still buffered in edge device video buffer, constituting non-negligible energy consumption. Beyond energy issues, edge video data has been increasingly applied in safety–critical scenarios, where reliability has also become a critical concern. Unlike the controlled accuracy sacrifice of the lossy compression mechanism, the high information content per bit may render compressed data more sensitive to random transient faults attacking (i.e., soft errors), thereby inducing severe safety hazards in some video processing tasks (e.g., autonomous vehicle collision).Thus, in this paper, we propose a “soft error efficient” on-the-fly compression mechanism named DUAL-C to achieve energy savings in edge device video buffer while maintaining data reliability. Firstly, observing the duplicate feature of upper bits and approximable characteristic of lower bits within the camera sensors generated streaming raw pixel blocks, we design two compressing techniques: DU-C extracts the common duplicate upper-bits while AL-C merely stores one representative approximate lower-bits for all pixels within a block. By combining DU-C and AL-C with the Sampling-based Approximation paradigm (SA), DUAL-C achieves the overall energy consumption reduction of the video buffer by 71.31%. Secondly, to avoid the reliability “dark side” introduced by compression, we conduct a comprehensive error resilience analysis of compressed data and merely harden the error-critical control bits and common upper bits with ECC. Evaluation results show that DUAL-C compressed data exhibits even better error robustness than its uncompressed counterpart with negligible protection overhead.

Deep Joint Source-Channel Coding for DNA Image Storage: A Novel Approach With Enhanced Error Resilience and Biological Constraint Optimization

Deep Joint Source-Channel Coding for DNA Image Storage: A Novel Approach With Enhanced Error Resilience and Biological Constraint Optimization

Improving The Efficiency Of Video Transmission In Computer Networks

In-depth examination of current techniques for enhancing the efficiency of video transmission over digital networks is provided in this study. Due to the growing need for high-quality video content, optimizing video transmission is an important area of research. This review categorizes and in-depth examines a range of methods proposed in the literature to enhance video transmission effectiveness. ABR, DNN architecture, adaptive streaming, Quality of Service (QoS), error resilience, congestion control, video compression, and hardware acceleration for video provisioning are just a few of the cutting-edge techniques that are covered in the discussion, which ranges from the more traditional to the cutting-edge. This essay provides a methodical evaluation of the numerous tactics that are available, along with an analysis of their guiding principles, advantages, and disadvantages. The paper also offers a comparative analysis of various approaches, highlighting trends, gaps, and potential future research directions in this crucial domain, all of which help to create more efficient video compression and transmission paradigms in computer networks.

TC-SEPM: Characterizing soft error resilience of CNNs on Tensor Cores from program and microarchitecture perspectives

As an architectural CNN accelerator integrated into NVIDIA’s GPUs, existing research mainly focuses on improving the performance of Tensor Cores. However, the highly integrated Tensor Cores are vulnerable to transient faults (i.e., soft errors), causing catastrophic consequences in safety-critical applications like automatic driving. Thus, it is imperative to estimate the reliability of CNNs on Tensor Cores. However, obtaining a statistically significant resilience profile of CNNs on Tensor Cores with the existing fault injection (FI)-based reliability estimation methods is expensive. To this end, we build TC-SEPM to predict the error resilience of CNNs on Tensor Cores instead of FI methods. To ensure the accuracy of TC-SEPM, we first investigate resilience-related features from program and microarchitecture perspectives. Then, leveraging these heuristic features, we train machine learning models to learn the hidden relationship between error resilience and the investigated features, enabling us to predict the impact of soft errors in Tensor Cores on CNN output. Experimental results show that TC-SEPM achieves high accuracy for individual soft error resiliency prediction and overall program resilience estimation while its overhead is only 1/27 of FI methods. Additionally, TC-SEPM can provide valuable insights for programmers or architects to design more robust CNN models on Tensor Cores.

HIPEDAP: Energy-Efficient Hardware Accelerators for Hidden Periodicity Detection

Hidden periodicity detection (HPD) forms the basis of various emerging and complex applications such as detecting tandem repeats in DNA and protein, absence seizure detection in EEG signals, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">etc.</i> The various solutions to the period estimation problem were not satisfactorily accurate until Ramanujan sums (RS) were recently used to explore the idea of periodic decomposition of signals. The use of Ramanujan sums in hidden periodicity detection was streamlined to form Ramanujan Filter Bank (RFB), but even then its usage in the applications proved to be computationally expensive. This paper proposes HIPED <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AP</sub> , an efficient set of hardware accelerators for hidden periodicity detection applications using Ramanujan Filter Bank. HIPED <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AP</sub> is developed by proposing several incrementally efficient microarchitectures targeting improvements in different aspects of the design such as area, power, and performance. We first propose a basic microarchitecture for the accelerator, Arch-A, which we then optimize and improve in terms of area, frequency of execution or power, in incremental steps to obtain Arch-E. These design improvements stem from various optimization techniques such as different filter structure realizations, transposition, pipelining and implementation of a fast division circuit. Further, the inherent error resilience exhibited by HPD applications enables us to propose an approximate architecture, Arch-F, that synergistically applies multiple approximation techniques such as approximate adder, multiplier, and precision scaling on top of Arch-E, resulting in significant performance and energy benefits. Experimental results obtained after synthesizing and mapping the hardware implementation of the microarchitectures on 45 nm technology demonstrate that the optimized Arch-E design is able to achieve 4.7X, 8.2X and 1.7X improvements over Arch-A in terms of area, frequency of execution and power, respectively. On top of this, the approximate Arch-F design demonstrated additional power savings of 14.6% on average (and upto 32.2%) over Arch-E for almost no loss in application-level quality. Finally, across a suite of practical applications, HIPED <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AP</sub> exhibited a speed-up in the range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$5.1 {\times } 10^{2}$</tex-math></inline-formula> X to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$3.2 {\times } 10^{4}$</tex-math></inline-formula> X with a geometric mean of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$3.7 {\times } 10^{3}$</tex-math></inline-formula> X compared to its software implementations.

Approximate Computing: Hardware and Software Techniques, Tools and Their Applications

The limitations of scaling in CMOS technology pose challenges in meeting the requirements of future applications. To address these challenges, researchers are exploring various design techniques, including Approximate Computing (AC), which leverages the inherent error resilience of applications to achieve high performance and energy gains with desired quality. AC has gained popularity as a computer paradigm for error-resilient applications, and many researchers have studied AC across computing layers and developed tools for implementing these techniques. This paper provides a comprehensive survey of AC techniques at the abstraction levels of software and hardware and discusses the tools to implement AC in hardware and software, quality evaluation tools and comparison points. The paper also covers existing frameworks for AC, potential applications, future research directions, challenges and limitations. This information can guide researchers in identifying promising avenues for further advancements and innovations in this domain. Additionally, this paper compares state-of-the-art surveys of AC and highlights the unique features and contributions of this work that distinguish our work from previous surveys.

AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA

With the inherent algorithmic error resilience of conventional neural networks (CNN) and the worst-case design methodologies of current electronic design automation tools, overclocking-based timing speculation is a promising technique to improve the performance of CNN accelerators on FPGA by removing unnecessary timing margins. To avoid potential timing errors, timing delay measurement should be used during overclocking. However, current approaches are not yet good at measuring paths with more intense variability factors such as jitter, and lack an automated process for testing circuit delays. In this paper, we first propose 2-dimension multi-frame fusion to deal with the sampling jitter, then present a timing delay measurement-based automatic overclocking system (AOS) running on heterogeneous FPGA for high-performance CNN accelerators. On the FPGA side, AOS is composed of timing delay monitors (TDM) that can measure all types of timing paths, a TDM controller that converts the sampled values of TDMs into timing delay in terms of the ratio of path delay to the clock period. On the CPU side, AOS converts the path delay from clock period ratio to absolute delay value and decides the frequency of the accelerator in the next iteration. We demonstrate AOS with a SkyNet accelerator on the Xilinx ZCU104 board and achieve 657FPS at 436MHz without accuracy degradation, which is 1.41× performance compared to the baseline.

Common lossless compression algorithms and their error resiliency performance

With the development of communication technology and computer technology, many related industries, such as multimedia entertainment, put forward higher requirements for storing and transmitting information data. The research of data compression technology has attracted more and more attention. Therefore, the error resiliency ability of data compression algorithm is particularly important. How to enhance the error resiliency of data compression communication systems has been a hot topic for researchers. This paper mainly introduces the lossless data compression technology and its basic principle and performance index. Two typical lossless compression codes, Huffman and Arithmetic coding are deeply studied, including the principle of coding and the problem of error resiliency. Huffman coding and Arithmetic coding are two very important lossless compression codes widely used. The ability to resist channel error is an important index for data compression in communication. It is of great significance to further improve the channel adaptability of data compression to study the above two kinds of codes and their ability to resist channel error.

High-resolution CMOS-based biosensor for assessing hippocampal circuit dynamics in experience-dependent plasticity

Experiential richness creates tissue-level changes and synaptic plasticity as patterns emerge from rhythmic spatiotemporal activity of large interconnected neuronal assemblies. Despite numerous experimental and computational approaches at different scales, the precise impact of experience on network-wide computational dynamics remains inaccessible due to the lack of applicable large-scale recording methodology. We here demonstrate a large-scale multi-site biohybrid brain circuity on-CMOS-based biosensor with an unprecedented spatiotemporal resolution of 4096 microelectrodes, which allows simultaneous electrophysiological assessment across the entire hippocampal-cortical subnetworks from mice living in an enriched environment (ENR) and standard-housed (SD) conditions. Our platform, empowered with various computational analyses, reveals environmental enrichment's impacts on local and global spatiotemporal neural dynamics, firing synchrony, topological network complexity, and large-scale connectome. Our results delineate the distinct role of prior experience in enhancing multiplexed dimensional coding formed by neuronal ensembles and error tolerance and resilience to random failures compared to standard conditions. The scope and depth of these effects highlight the critical role of high-density, large-scale biosensors to provide a new understanding of the computational dynamics and information processing in multimodal physiological and experience-dependent plasticity conditions and their role in higher brain functions. Knowledge of these large-scale dynamics can inspire the development of biologically plausible computational models and computational artificial intelligence networks and expand the reach of neuromorphic brain-inspired computing into new applications.

Error-Resilient Data Compression With Tunstall Codes

Data compression has been commonly employed to reduce the required memory size for emerging applications with large storage needs like Big Data and Machine Learning (ML). When considering the flexibility of decompression and its hardware implementation, variable-to-fixed length codes (e.g., Tunstall codes) are usually selected. However, memories are prone to suffer different types of errors, causing the stored data to be corrupted; if an error affects the compressed data, it can propagate and cause corruption in a sequence of bits of the decompressed data. Therefore, error resilience should be built-in as part of the memory design to provide reliable data, especially for safety-critical applications. However, Error Correction Codes (ECCs) that are widely used for memory protection, are not very efficient to protect compressed data, because ECCs further increase the memory size and the additional decoding process can impact the latency to decompress the stored data. In this paper, an efficient error-resilient data compression technique with Tunstall codes is proposed; it requires almost no memory overhead and can correct most errors during the decompression process by introducing a conversion table. An enhanced design is also presented to reduce the impact of errors when they cannot be corrected. The proposed scheme has been implemented and evaluated on three ML datasets; results show that it can deal with up to 99.98% errors with almost no memory overhead when Tunstall codes with smaller than 16-bit symbols are employed. The scheme has also been evaluated for two ML applications; results show that even though a small number of errors cannot be corrected in the proposed scheme, they have an extremely low impact on the classification results and the protection overhead is significantly lower than existing ECC techniques

Ensuring High Data Quality and Error Resilience in Autonomous Self-Schedulable Libraries for Heterogeneous Data Sources in NearReal-Time Ingestion Pipelines

Ensuring High Data Quality and Error Resilience in Autonomous Self-Schedulable Libraries for Heterogeneous Data Sources in NearReal-Time Ingestion Pipelines

Fast Quantifier of High‐Dimensional Frequency Entanglement through Hong–Ou–Mandel Interference

AbstractHigh‐dimensional frequency entanglement is an enabling resource in quantum technology due to its high information capacity and error resilience. A concise yet efficient method for precisely quantifying its dimensionality remains an open challenge, owing to the difficulties for performing required superposition measurements in energy‐time domains, and the complexity associated with full quantum state tomography that scales unfavorably with dimensions. With the assistance of Hong–Ou–Mandel experiment that performs a Fourier transform between the entangled photons in terms of joint spectral intensities and the quantum interference in terms of biphoton temporal coincidences, the concept of Shannon dimensionality as a fast quantifier of bipartite continuous frequency entanglement is unlocked. This quantitative technique reveals the complete distribution of frequency entanglement but without suffering from any limitation of modal capacity of the detection geometry. These results may significantly facilitate the use of quantum interference for characterizing the high‐dimensional entanglement nature by avoiding some stringent conditions.

Smart Multi-Agent Framework for Automated Audio Testing

With the widespread use of embedded software in consumer electronics, automotive industry, medical devices, and industrial environments, embedded software testing is gaining significance as an indispensable part of development and deployment of embedded products. With more than 20 years of research, development, and testing of various consumer technologies and products based on digital signal processors (DSPs) and advanced reduced instruction set computers (ARMs), we obtained insight into typical embedded development process and testing, and the pros and cons of various testing approaches and environments. In this paper, we propose the Smart Multi-Agent Framework based on IoT and Jenkins agents, customised for audio technologies in the Home Audio domain. We evaluated our solution on several complex immersive audio technologies implemented on a multicore DSP. Our uniform, customised, fully automated approach proved to be time efficient, error resilient, easy to replicate and use across all development, certification, and deployment phases of the product life cycle.