HIPEDAP: Energy-Efficient Hardware Accelerators for Hidden Periodicity Detection

Abstract

Hidden periodicity detection (HPD) forms the basis of various emerging and complex applications such as detecting tandem repeats in DNA and protein, absence seizure detection in EEG signals, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">etc.</i> The various solutions to the period estimation problem were not satisfactorily accurate until Ramanujan sums (RS) were recently used to explore the idea of periodic decomposition of signals. The use of Ramanujan sums in hidden periodicity detection was streamlined to form Ramanujan Filter Bank (RFB), but even then its usage in the applications proved to be computationally expensive. This paper proposes HIPED <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AP</sub> , an efficient set of hardware accelerators for hidden periodicity detection applications using Ramanujan Filter Bank. HIPED <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AP</sub> is developed by proposing several incrementally efficient microarchitectures targeting improvements in different aspects of the design such as area, power, and performance. We first propose a basic microarchitecture for the accelerator, Arch-A, which we then optimize and improve in terms of area, frequency of execution or power, in incremental steps to obtain Arch-E. These design improvements stem from various optimization techniques such as different filter structure realizations, transposition, pipelining and implementation of a fast division circuit. Further, the inherent error resilience exhibited by HPD applications enables us to propose an approximate architecture, Arch-F, that synergistically applies multiple approximation techniques such as approximate adder, multiplier, and precision scaling on top of Arch-E, resulting in significant performance and energy benefits. Experimental results obtained after synthesizing and mapping the hardware implementation of the microarchitectures on 45 nm technology demonstrate that the optimized Arch-E design is able to achieve 4.7X, 8.2X and 1.7X improvements over Arch-A in terms of area, frequency of execution and power, respectively. On top of this, the approximate Arch-F design demonstrated additional power savings of 14.6% on average (and upto 32.2%) over Arch-E for almost no loss in application-level quality. Finally, across a suite of practical applications, HIPED <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AP</sub> exhibited a speed-up in the range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$5.1 {\times } 10^{2}$</tex-math></inline-formula> X to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$3.2 {\times } 10^{4}$</tex-math></inline-formula> X with a geometric mean of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$3.7 {\times } 10^{3}$</tex-math></inline-formula> X compared to its software implementations.