Error Resilience Research Articles

Approximate Spintronic Memories

Various applications, such as multimedia, machine learning, and signal processing, have a significant intrinsic error resilience. This makes them preferable for approximate computing as they have the ability to tolerate computations and data errors along with producing acceptable outputs. From the technology perspective, emerging technologies with inherent non-determinism and high failure rates are candidates for the realization of approximate computing. Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) is an emerging non-volatile memory technology and a potential candidate to replace SRAM due to its high density, scalability, and zero-leakage. The write operation in this technology is inherently stochastic and increases the rate of write errors. Moreover, this technology is associated with other failure mechanisms such as read-disturb and failures due to data retention. These errors are highly dependent on the STT-MRAM parameters (i.e., thermal stability, read/write current, and read/write latency), which varies with the operating temperature and the process variation effects. Fast and energy-efficient STT-MRAM designed for on-chip memories can be easily achieved by relaxing the device parameters at the cost of increased error rate, which can be addressed by approximating memory accesses. In this work, a detailed study of reliability and gains (i.e., performance and energy) tradeoff at the device and system-level of the STT-MRAM-based data cache system is presented in the scope of approximate memories.

Adaptive Bitrate Video Transmission Over Cognitive Radio Networks Using Cross Layer Routing Approach

Due to the recent developments in the wireless mesh and ad-hoc networks, multi-hop cognitive radio networks (MCRNs) have attained the significant attention towards providing the reliable multimedia communications. However, in reliable multimedia communications each multimedia application observed a very stringent quality-of-service (QoS) requirements. Moreover, in MCRNs, channel allocated to the multimedia secondary users (MSUs) can be re-occupied by the primary users (PUs) at any time which causes the end-to-end path discontinuity that severely affect the performance of the MCRNs. Therefore, under the dynamic channel availability, selecting an end-to-end path that is not only stable but also fulfills the QoS requirements of the real time and multimedia (RM) applications is a challenging task and still an open research problem. Hence, in this paper, we propose a cross-layer routing scheme that supports adaptive bit-rate multimedia (ABM) transmissions over MCRNs. Moreover, our path selection is based on the QoS-aware end-to-end path delay, and PU-activity aware end-to-end path stability metrices. Furthermore, to avoid the PU interference, continuity in transmission, efficient channel utilization, and supporting error resilience over time varying wireless channels our selected end-to-end path is periodically updated. Simulation study shows that the proposed scheme is more robust and suitable for supporting ABM over MCRNs.

An adaptive, cross layer error control scheme for Distributed Video Coding over Wireless Multimedia Sensor Networks

Distributed Video Coding with low computational complexity at the encoder side has a high potential for use in Wireless Multimedia Sensor Networks. However, the different architecture of this coding and resource constraints in WMSNs require the design of new efficient transmission protocols for transmission of DVC through WMSNs. In view of these protocols, error control mechanisms have more importance in reliable multimedia communication over WMSN. These mechanisms provide higher video quality in receiver nodes while saving the energy of sender nodes by the reliable transmission of packets. Given the importance of this issue, in this paper, we propose an adaptive, cross-layer error control scheme to protect video frames in the transmission of DVC over WMSN, which serves QOS while considering energy consumption and frames’ delay constraints. To propose this scheme, we used the accurate results from our previous works on error resiliency of DVC and comparative performance analysis of error control methods for this codec. The proposed scheme has been analyzed and compared to all standard, layer and, multi-layer error control schemes against the most important criteria in video communication over WSNs such as energy consumption, delay, and PSNR. Simulation results show that this scheme saves the quality of video in different channel conditions by consuming the least possible amount of energy based on the maximum allowable delay at the receiver.

A Novel Data-Aided Frame Synchronization Method Based on Hough Transform for Optical Communications

In optical communication systems, frame synchronization is essential for subsequent operations, such as error correction and payload extraction. Various methods, so far, have been proposed in the published literature, but the performance is unsatisfactory under high bit error rate (BER) conditions. We present, in this work, a novel data-aided frame synchronization technique for optical packet transmission systems, in which the transmitter sends a sequence of packets with a specific synchronization word periodically inserted, and the receiver blindly recognizes the synchronization word to attain frame synchronization. The proposed algorithm detects the synchronization word based on Hough transform (HT), a classic method for line detection in digital image processing. The core principle of the algorithm is to exploit the periodicity of the frame synchronization word, which appears as black-and-white spaced stripes on a binary image when the frames are all aligned. Simulations are conducted over a 56Gbps optical QPSK transmission system, and the results show that our algorithm is still effective in attaining frame synchronization at a BER of 0.3. A comparison is also made between our algorithm and existed autocorrelation (AC)-based algorithm. The results demonstrate that our algorithm has a better error resilience performance. When the BER is higher than 0.03, our algorithm outperforms an AC-based algorithm significantly.

Power optimized SRAM cell with high radiation hardened for aerospace applications

The SRAM cells suffer from soft errors under high radiation environment like aerospace and satellite applications. Few radiations hardened based popular cells are 12T Dice and 12T We-Quatro. But these cells required more area and power consumption. To address these problems a 10T SRAM cell is designed, which gives perfect balance among all the parameters with higher delay. Hence, it is the most suggestible cell under high radiation environment. However, the 10T SRAM cell for high frequency under process variations gives a large number of write failure, which impeding the application of 10T SRAM cell. In this paper, a new SRAM cell has been proposed, which provides less power, more stability, less area, and very high soft error resilience. The proposed cell provides 17.48%, 5.26% less static power loss compared to We-Quatro and Dice, respectively. The total power loss of the proposed cell is reduced by 39.26%, 9.56% compared to We-Quatro and Dice cell respectively. The hold stability is increased by 45%, 81.59% compared to We-Quatro and Dice cell respectively. Also, the proposed cell gives moderate area overhead, comparable write speed, and perfect balance among all the parameters. The proposed cell is also verified using Monte Carlo (M.C) simulation in 45 nm CMOS technology.

Radiation Hardened Latch Designs for Double and Triple Node Upsets

As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously, work has been done to harden latches against single event upsets (SEU). Currently, there has been a concerted effort to design latches that are tolerant to double node upsets (DNU) and triple node upsets (TNU). In this paper, we first propose a novel DNU tolerant latch design. The latch is designed specifically to provide additional reliability when clock gating is used. Through experimentation, it is shown that the DNU tolerant latch is 11.3 percent more power efficient than existing latch designs suited for clock gating. In addition to the DNU tolerant design, we propose the first TNU tolerant latch. The TNU tolerant latch is shown to provide superior soft error resiliency while incurring a 40 percent overhead compared to DNU tolerant designs.

Design and Analysis of Secure and Dependable Automotive CPS: A Steer-by-Wire Case Study

The next generation of automobiles (also known as cybercars) will increasingly incorporate electronic control units (ECUs) in novel automotive control applications. Recent work has demonstrated the vulnerability of modern car control systems to security attacks that directly impacts the cybercar's physical safety and dependability. In this paper, we provide an integrated approach for the design of secure and dependable automotive cyber-physical systems (CPS) using a case study: a steer-by-wire (SBW) application over controller area network (CAN). The challenge is to embed both security and dependability over CAN while ensuring that the real-time constraints of the automotive CPS are not violated. Our approach enables early design feasibility analysis of automotive CPS by embedding essential security primitives (i.e., confidentiality, integrity, and authentication) over CAN subject to the real-time constraints imposed by the desired quality of service and behavioral reliability. Our method leverages multicore ECUs for providing fault tolerance by redundant multi-threading (RMT) and also further enhances RMT for quick error detection and correction. We quantify the error resilience of our approach and evaluate the interplay of performance, fault tolerance, security, and scalability for our SBW case study.

GreenTPU: Predictive Design Paradigm for Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit

The emergence of hardware accelerators has brought about several orders of magnitude improvement in the speed of the deep neural-network (DNN) inference. Among such DNN accelerators, the Google tensor processing unit (TPU) has transpired to be the best-in-class, offering more than $15\times $ speedup over the contemporary GPUs. However, the rapid growth in several DNN workloads conspires to escalate the energy consumptions of the TPU-based data-centers. In order to restrict the energy consumption of TPUs, we propose GreenTPU—a low-power near-threshold (NTC) TPU design paradigm. To ensure a high inference accuracy at a low-voltage operation, GreenTPU identifies the patterns in the error-causing activation sequences in the systolic array, and prevents further timing errors from similar patterns by intermittently boosting the operating voltage of the specific multiplier-and-accumulator units in the TPU. Compared to a cutting-edge timing error mitigation technique for TPUs, GreenTPU enables $2\times $ to $3\times $ higher performance (TOPS) in an NTC TPU, with a minimal loss in the prediction accuracy.

Approximate Digital Leaky Integrate-and-fire Neurons for Energy Efficient Spiking Neural Networks

Inherent error resilience in neuromorphic computing allows remarkable power and energy savings by exploiting approximate computing. This paper presents approximate digital leaky integrate-and-fire (LIF) neurons that leverage the approximate adders for energy efficient spiking neural networks (SNNs). Various approximate adder architectures were assessed and adopted in designing a digital LIF neuron. To demonstrate the performance of the approximate LIF neurons, a two-layer SNN with more than 1,000 digital neurons were used with the approximate adders. The results showed that the approximation errors of the lower-part OR adder (LOA) and optimized lower-part constant OR adder (OLOCA) do not affect the neuron’s spiking activities of the network significantly. In addition, they showed good power and energy efficiency. The results suggest that the LOA and OLOCA are more suitable for SNNs to achieve power- and energyefficient neuromorphic computing than the other approximate adders.

Automated design of error-resilient and hardware-efficient deep neural networks

Applying deep neural networks (DNNs) in mobile and safety-critical systems, such as autonomous vehicles, demands a reliable and efficient execution on hardware. The design of the neural architecture has a large influence on the achievable efficiency and bit error resilience of the network on hardware. Since there are numerous design choices for the architecture of DNNs, with partially opposing effects on the preferred characteristics (such as small error rates at low latency), multi-objective optimization strategies are necessary. In this paper, we develop an evolutionary optimization technique for the automated design of hardware-optimized DNN architectures. For this purpose, we derive a set of inexpensively computable objective functions, which enable the fast evaluation of DNN architectures with respect to their hardware efficiency and error resilience. We observe a strong correlation between predicted error resilience and actual measurements obtained from fault injection simulations. Furthermore, we analyze two different quantization schemes for efficient DNN computation and find one providing a significantly higher error resilience compared to the other. Finally, a comparison of the architectures provided by our algorithm with the popular MobileNetV2 and NASNet-A models reveals an up to seven times improved bit error resilience of our models. We are the first to combine error resilience, efficiency, and performance optimization in a neural architecture search framework.

A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

Practical Resilience Analysis of GPGPU Applications in the Presence of Single- and Multi-Bit Faults

Graphics Processing Units (GPUs) have rapidly evolved to enable energy-efficient data-parallel computing for a broad range of scientific areas. While GPUs achieve exascale performance at a stringent power budget, they are also susceptible to soft errors, often caused by high-energy particle strikes, that can significantly affect the application output quality. Understanding the resilience of general purpose GPU (GPGPU) applications is especially challenging because unlike CPU applications, which are mostly single-threaded, GPGPU applications can contain hundreds to thousands of threads, resulting in a tremendously large fault site space in the order of billions, even for some simple applications and even when considering the occurrence of just a single-bit fault. We present a systematic way to progressively prune the fault site space aiming to dramatically reduce the number of fault injections such that assessment for GPGPU application error resilience becomes practical. The key insight behind our proposed methodology stems from the fact that while GPGPU applications spawn a lot of threads, many of them execute the same set of instructions. Therefore, several fault sites are redundant and can be pruned by careful analysis. We identify important features across a set of 10 applications (16 kernels) from Rodinia and Polybench suites and conclude that threads can be primarily classified based on the number of the dynamic instructions they execute. We therefore achieve significant fault site reduction by analyzing only a small subset of threads that are representative of the dynamic instruction behavior (and therefore error resilience behavior) of the GPGPU applications. Further pruning is achieved by identifying the dynamic instruction commonalities (and differences) across code blocks within this representative set of threads, a subset of loop iterations within the representative threads, and a subset of destination register bit positions. The above steps result in a tremendous reduction of fault sites by up to seven orders of magnitude. Yet, this reduced fault site space accurately captures the error resilience profile of GPGPU applications. We show the effectiveness of the proposed progressive pruning technique for a single-bit model and illustrate its application to even more challenging cases with three distinct multi-bit fault models.

Soft error hardening enhancement analysis of NBTI tolerant Schmitt trigger circuit

Bias temperature instability (BTI) and soft errors are major reliability concerns for deep submicron technologies. Negative BTI leads to an increase of the threshold voltage of PMOS transistors and is thus considered a serious challenge for improving circuit performance. In this paper, we concentrate on a design-time solution, i.e., more reliable NMOS only Schmitt Trigger with Voltage Booster (NST-VB). For this we analyzed the impact of BTI on the soft-error susceptibility of different CMOS circuits using HSPICE and performed critical charge simulations considering different supply voltages and stress time. From our results, we conclude that the NST-VB circuit has a higher critical charge when compared to CMOS inverters and Schmitt trigger (ST) based counterparts. NST-VB has improved the sensitivity of 62.48% and 55.10%, as compared to CMOS inverter and ST circuits, respectively, after three years of operation. To better assess soft error resilience, we introduce a soft error rate ratio (SERR) as a performance metric. Our analysis indicates that NST-VB has 12.62%, and 12.39% less SERR compared to ST and CMOS inverters. The effect of process variation on CMOS inverter, ST inverter and NST-VB circuit are analyzed using 5000 Monte Carlo simulations for critical voltages and we observe that the deviation of NST-VB is 6.06× and 6.89× less as compared to the CMOS and ST based inverters, respectively.

Security techniques for intelligent spam sensing and anomaly detection in online social platforms

The recent advances in communication and mobile technologies made it easier to access and share information for most people worldwide. Among the most powerful information spreading platforms are the Online Social Networks (OSN)s that allow Internet-connected users to share different information such as instant messages, tweets, photos, and videos. Adding to that many governmental and private institutions use the OSNs such as Twitter for official announcements. Consequently, there is a tremendous need to provide the required level of security for OSN users. However, there are many challenges due to the different protocols and variety of mobile apps used to access OSNs. Therefore, traditional security techniques fail to provide the needed security and privacy, and more intelligence is required. Computational intelligence adds high-speed computation, fault tolerance, adaptability, and error resilience when used to ensure security in OSN apps. This research provides a comprehensive related work survey and investigates the application of artificial neural networks for intrusion detection systems and spam filtering for OSNs. In addition, we use the concept of social graphs and weighted cliques in the detection of suspicious behavior of certain online groups and to prevent further planned actions such as cyber/terrorist attacks before they happen.

RETRACTED: Efficient soft error resiliency by multi-match packet classification using scalable TCAM implementation in FPGA

Ternary content addressable memories (TCAMs) are generally utilized for system gadgets to actualize parcel characterization. They are utilized, for instance, for bundle sending, for security, and to actualize programming characterized systems (SDNs). TCAMs are normally executed as independent gadgets or as a protected innovation obstruct that is coordinated on systems administration application-explicit incorporated circuits. Then again, field-programmable entryway exhibits (FPGAs) excluding TCAM squares. Be that as it may, the adaptability of FPGAs impacts in alluring for SDN usage, and majority of field programmable gate array merchants give improvement packs to SDN. By considering implementation of TCAM in FPGA and, hence, there is an importance to imitate TCAMs utilizing the rationale squares possible to be reached in the FPGA. Lately, various plans to imitate TCAMs on FPGAs have been devised. Least among them exploit the major of memory squares accessible into the inner part of present day FPGAs to utilize them to execute TCAMs. An issue when utilizing recollections is that those squares will be influenced by delicate blunders that degenerate the put away bits. The recollections can be secured with an equality test to distinguish blunders or with a mistake redress code to address them, yet it needs extra bits of memory for each word. Regarding the above concise, the insurance of the recollections used to imitate new TCAM has been implemented. Specifically, it is appeared by abusing the way that just a subset of the conceivable memory substance are legitimate, most single-piece blunders can be redressed when the recollections are ensured with an equality bit.

Error metrics determination in functionally approximated circuits using SAT solvers.

Approximate computing is an emerging design paradigm that offers trade-offs between output accuracy and computation efforts by exploiting some applications’ intrinsic error resiliency. Computation of error metrics is of paramount importance in approximate circuits to measure the degree of approximation. Most of the existing techniques for evaluating error metrics apply simulations which may not be effective for evaluation of large complex designs because of an immense increase in simulation runtime and a decrease in accuracy. To address these deficiencies, we present a novel methodology that employs SAT (Boolean satisfiability) solvers for fast and accurate determination of error metrics specifically for the calculation of an average-case error and the maximum error rate in functionally approximated circuits. The proposed approach identifies the set of all errors producing assignments to gauge the quality of approximate circuits for real-life applications. Additionally, the proposed approach provides a test generation method to facilitate design choices, and acts as an important guide to debug the approximate circuits to discover and locate the errors. The effectiveness of the approach is demonstrated by evaluating the error metrics of several benchmark-approximated adders of different sizes. Experimental results on benchmark circuits show that the proposed SAT-based methodology accurately determines the maximum error rate and an average-case error within acceptable CPU execution time in one go, and further provides a log of error-generating input assignments.

SLEPX: An Efficient Lightweight Cipher for Visual Protection of Scalable HEVC Extension

This paper proposes a lightweight cipher scheme aimed at the scalable extension of the High Efficiency Video Coding (HEVC) codec, referred to as the Scalable HEVC (SHVC) standard. This stream cipher, Symmetric Cipher for Lightweight Encryption based on Permutation and EXlusive OR (SLEPX), applies Selective Encryption (SE) over suitable coding syntax elements in the SHVC layers. This is achieved minimal computational complexity and delay. The algorithm also conserves most SHVC functionalities, i.e. preservation of bit-length, decoder format-compliance, and error resilience. For comparative analysis, results were taken and compared with other state-of-art ciphers i.e. Exclusive-OR (XOR) and the Advanced Encryption Standard (AES). The performance of SLEPX is also compared with existing video SE solutions to confirm the efficiency of the adopted scheme. The experimental results demonstrate that SLEPX is as secure as AES in terms of visual protection, while computationally efficient comparable with a basic XOR cipher. Visual quality assessment, security analysis and extensive cryptanalysis (based on numerical values of selected binstrings) also showed the effectiveness of SLEPX's visual protection scheme for SHVC compared to previously-employed cryptographic techniques.

An Analysis on Tradable Permit Models for Last-Mile Delivery Drones

Drones can play a game-changing role in reducing both cost and time in the context of last-mile deliveries. This paper addresses the last-mile delivery problem from a complex system viewpoint, where the collective performance of the drones is investigated. We consider a last-mile delivery system with a tradable permit model (TPM) for airspace use. Typically, in other research works regarding last-mile delivery drones, a fully cooperative centralized scenario is contemplated. In our approach, due to the TPM, the agents (i.e. drones) need to compete for airspace permits in a distributed manner. We simulate the system and evaluate how different parameters, such as the arrival rate and airspace dimensions, impact the system behavior in terms of the cost and time needed by the drones to acquire flight permits, and the airspace utilization. We use a simplified simulation model, where the agents' strategies are naïve, and the drones' flight dynamics are not accounted for. Nevertheless, the simulation's level of detail is adequate for capturing interesting properties from the agents' collective behavior, as our results support. The obtained results show that the system's performance is satisfactory, even with naïve agents and under high traffic conditions. Moreover, a real-world implementation of our competitive decentralized approach would lead to advantages, such as fast permit transactions, simple computational infrastructures, and error resilience.

Towards a Low Complexity Scheme for Medical Images in Scalable Video Coding

Medical imaging has become of vital importance for diagnosing diseases and conducting noninvasive procedures. Advances in eHealth applications are challenged by the fact that Digital Imaging and Communications in Medicine (DICOM) requires high-resolution images, thereby increasing their size and the associated computational complexity, particularly when these images are communicated over IP and wireless networks. Therefore, medical research requires an efficient coding technique to achieve high-quality and low-complexity images with error-resilient features. In this study, we propose an improved coding scheme that exploits the content features of encoded videos with low complexity combined with flexible macroblock ordering for error resilience. We identify the homogeneous region in which the search for optimal macroblock modes is early terminated. For non-homogeneous regions, the integration of smaller blocks is employed only if the vector difference is less than the threshold. Results confirm that the proposed technique achieves a considerable performance improvement compared with existing schemes in terms of reducing the computational complexity without compromising the bit-rate and peak signal-to-noise ratio.

Soft Error Resilience of Deep Residual Networks for Object Recognition

Convolutional Neural Networks (CNNs) have truly gained attention in object recognition and object classification in particular. When being implemented on Graphics Processing Units (GPUs), deeper networks are more accurate than shallow ones. Residual Networks (ResNets) are one of the deepest CNN architectures used in various fields including safety-critical ones. GPUs have proven to be the major accelerator for CNN models. However, modern GPUs are prone to radiation-induced soft errors, which is a serious issue in safety-compliant systems. In this work, we analyze and propose an approach to address the reliability of ResNet on GPUs. We firstly analyze three popular ResNet models, explicitly, ResNet-50, ResNet-101, and ResNet-152 through NVIDIA's fault injector, SASSIFI. We perform an in-depth analysis of the model from the perspective of layer and kernel vulnerability. Then, we experimentally show the vulnerability of ResNet models and identify the most vulnerable portions. Finally, we validate our solution, which is a selective-hardening technique, through hardening the worth-hardening kernels to avoid unnecessary overheads. Our strategy is demonstrated to mask up to 93.38% of the injected errors with performance overhead less than 5.35%. Furthermore, the percentage of the errors causing misclassifications can be reduced from 4.2% to 0.104%, thereby significantly improving the model's reliability.