Error Detection Codes Research Articles

Automated Quantum Circuit Design With Nested Monte Carlo Tree Search

Quantum algorithms based on variational approaches are one of the most promising methods to construct quantum solutions and have found a myriad of applications in the last few years. Despite the adaptability and simplicity, their scalability and the selection of suitable ansatzes remain key challenges. In this work, we report an algorithmic framework based on nested Monte-Carlo Tree Search (MCTS) coupled with the combinatorial multi-armed bandit (CMAB) model for the automated design of quantum circuits. Through numerical experiments, we demonstrate our algorithm applied to various kinds of problems, including the ground energy problem in quantum chemistry, quantum optimisation on a graph, solving systems of linear equations, and finding encoding circuits for quantum error detection codes. Compared to the existing approaches, the results indicate that our circuit design algorithm can explore larger search spaces and optimise quantum circuits for larger systems, showing both versatility and scalability.

VLSI Implementation of Multi-Bit Error Detection and Correction Codes for Space Communications

VLSI Implementation of Multi-Bit Error Detection and Correction Codes for Space Communications

Machine learning FSO-SAC-OCDMA code recognition under different weather conditions

Nowadays, transmitting and receiving data with high speed and a high level of security are the main demands. So, a new model of spectral amplitude coding optical code division multiple access (SAC-OCDMA) is suggested in this paper, based on a free space optical (FSO) communication system using coherent sources. Three different codes: enhanced double weight (EDW), modified double weight (MDW) and multi-diagonal (MD) codes are assigned to our proposed model with the direct detection (DD) technique. Furthermore, the model is simulated under different weather conditions including clear air (CA), light mist (LM), very light fog, and light fog (LF). The system performance is evaluated through its bit error rate (BER), Q-factor, received power, and signal to noise ratio (SNR). Moreover, classification of the information received by the three different SAC-OCDMA using three different codes (EDW, MDW, and MD) is still challenging. So, two different machine learning (ML) algorithms are used, in this study, to classify the data received using the different codes. Detecting which code is received at the receiver end is important in order to reduce code error detection. Two algorithms: K-Nearest Neighbor (KNN) and Support Vector Machine (SVM) are adopted to classify different codes used for data transmission under four different weather conditions. The ML input dataset consists of the obtained simulation results, including Q-factor, BER, and SNR. Each feature is to be normalized before using ML. The obtained results show that the performance of the proposed FSO model achieved the longest propagation range under CA weather conditions, 7 km, while the shortest is under LF, which is 0.98 km. This is due to the attenuation of fog that causes signal degradation. The FSO system that uses EDW gives the best result under different weather conditions, while the system that uses MD code gives the worst performance. Also, the highest power is achieved when the EDW code is used at 5.5 km. The EDW has a received power of − 21.58 dBm, while the received power is − 22.04 dBm and − 23.8 dBm for MDW and MD codes, respectively. As for classification between the received information coming from three different codes under different weather conditions, both algorithms, KNN and SVM, achieve promising results in most cases. They showed more than 97% of classification accuracy under CA, LM, and LF weather conditions.

Codes for Compression and Error Detection

This article summarizes the main results about codes that combine the data compression power of Huffman trees with the error detection mechanisms proposed by Hamming. Two methods are described: the even trees method and the Hamming-Huffman trees method. Most of the works are the result of a close collaboration with Jayme Luiz Szwarcfiter.

Low-Power VLSI Implementation of Novel Hybrid Adaptive Variable-Rate and Recursive Systematic Convolutional Encoder for Resource Constrained Wireless Communication Systems

In the modern wireless communication system, digital technology has tremendous growth, and all the communication channels are slowly moving towards digital form. Wireless communication has to provide the reliable and efficient transfer of information between transmitter and receiver over a wireless channel. The channel coding technique is the best practical approach to delivering reliable communication for the end-users. Many conventional encoder and decoder units are used as error detection and correction codes in the digital communication system to overcome the multiple transient errors. The proposed convolutional encoder consists of both Recursive Systematic Convolutional (RSC) Encoder and Adaptive Variable-Rate Convolutional (AVRC) encoder. Adaptive Variable-Rate Convolutional encoder improves the bit error rate performance and is more suitable for a power-constrained wireless system to transfer the data. Recursive Systematic Convolutional encoder also reduces the bit error rate and improves the throughput by employing the trellis termination strategy. Here, AVRC encoder ultimately acquires the channel state information and feeds the data into a fixed rate convolutional encoder and rate adaptor followed by a buffer device. A hybrid encoder combines the AVRC encoder and RSC encoder output serially and parallel, producing the solid encoded data for the modulator in the communication system. A modified turbo code is also obtained by placing interleaver between the two encoder units and building the stronger code word for the system. Finally, the conventional encoder system is compared and analyzed with the proposed method regarding the number of LUT’s, gates, clock cycle, slices, area, power, bit error rate, and throughput.

Resource allocation in 5G network using Orthogonal Frequency Division Multiplexing‐Hybrid Automatic Repeat Request

SummaryFading, interference, and collisions cause unpredictable data loss in a wireless channel. In the recent past, the use of polar codes for error detection and correction scaled downed the data error rate considerably. With the introduction of 5G mobile network, minimizing the data loss and enhancing the performance becomes imperative. Here, the use of polar codes based OFDM‐HARQ mechanism with CRC is simulated and implemented. The proposed technique was tested for various fading channels. A bundling mechanism is used to attain the optimal number of retransmissions to accomplish better frame dropping ratio and throughput. It has been observed that the bit error rate of the proposed system has improved by optimizing Eb/No and bandwidth. At this optimum setting, the bit error rate has been enhanced by 25%. At the same time, the system optimizes retransmission count to a value of three, which improves frame error rate at the desirable bit error rate of 10−6. Further, the use of the proposed optimized polar code reduces complexity computations from one third to one fifth as compared to conventional system modeling using turbo codes. An enhancement in frame dropping ratio by 8% to 12% as well as throughput by 10.23% to 14.33% is achieved. The work carried on the hardware system shows that data loss in the OFDM‐HARQ communication system can be minimized by improving the bit error rate and throughput required for device‐to‐device communication in the 5G network.

Perancangan dan Implementasi Encoder dan Decoder CRC-8 untuk Pendeteksian Error pada Transmisi Data antar Perangkat IoT

Cyclic Redundancy Check (CRC) is a widely used error detection code in digital communication systems to detect errors in data transmitted between transmitter and receiver. With the development of Internet-of-Things (IoT) technology, where many devices communicate wirelessly, the application of error detection codes such as CRC is essential to obtain reliable communication. The computation of CRC can be implemented in hardware using a linear feedback shift register (LFSR) or in software with shift and bitwise exclusive OR (XOR) operations for polynomial division. Due to the frequent use of CRC in wireless communication for IoT, research for the design and implementation of CRC continues to this day. This study aims to design and implement the encoder and decoder of CRC-8 with generator polynomial 0x07 on IoT devices. Two algorithms for computing the CRC, namely bitwise computation using LFSR and another one using lookup tables, are implemented on the Arduino Uno R3 board. Two Arduino boards connected in serial were used to verify the encoder and decoder implementation in the data transmission and error detection process. The experiment results showed that the encoder could correctly calculate the CRC value from the input data. Furthermore, the computation using lookup tables takes about four times faster than the bitwise method but requires more memory. In contrast, the bitwise computation method requires less memory but slower computation time. When testing using input data of 128 characters, the bitwise-based encoder requires a computation time of 2.37 milliseconds, while the lookup table-based encoder utilizing a lookup table requires a computation time of 0.5 milliseconds. In the error detection test, the results demonstrated that the receiver could detect errors in the transmitted data with a percentage of 100%.

Demonstration of a general fault‐tolerant quantum error detection code for (2 n + 1)‐qubit entangled state on IBM 16‐qubit quantum computer

Quantum error detection has always been a fundamental challenge in a fault-tolerant quantum computer. Hence, it is of immense importance to detect and deal with arbitrary errors to efficiently perform quantum computation. Several error detection codes have been proposed and realised for lower number of qubit systems. Here we present an error detection code for a (2n + 1)-qubit entangled state using two syndrome qubits and simulate it on International Business Machines 16-qubit quantum computer for a 13-qubit entangled system. The code is able to detect an arbitrary quantum error in any one of the first 2n qubits of the (2n + 1)-qubit entangled state and detects any bit-flip error on the last qubit of the (2n + 1)-qubit entangled state via measurements on a pair of ancillary error syndrome qubits. The protocol presented here paves the way for designing error detection codes for the general higher number of entangled qubit systems.

Study of Different Types of Error Detection and Correction Code in Wireless Communication

The integrity of received data is a critical consideration in the design of digital communications and storage systems. The technique involved in attaining data reliability while transmission over a wireless channel is to use Channel Coding. These coding methods involve the use of Error Control Codes and there are two basic ways of controlling errors. They are Automatic Repeat Request and Forward Error Correction. This thesis concentrates on Forward error correction that deals with error detection and error correction. There are two types of error control codes: Block Codes and Convolutional Codes. The extent to which the errors are detected is a measure of the success of the code. The main trade-off in the error correction/detection technique lies in the key parameters involved in evaluating a coding system. Various block codes are analyzed using the performance metrics, namely, Improvement ratio and Error Resilience. It is observed that Cyclic Redundancy Check (CRC) codes showed better performance, and hence, they are chosen for further study.

Beware of Insufficient Redundancy

Fault injection attacks pose a serious threat to cryptographic implementations. Countermeasures beyond sensors and shields usually deploy some form of redundancy to detect or even correct errors. A few years ago, a novel design methodology called Impeccable Circuits has been introduced on how to correctly integrate Concurrent Error Detection (CED) schemes, based on Error-Detection Codes (EDCs), into cryptographic hardware circuits. The underlying adversary model limits attackers to inject at most t single-bit faults. By additionally considering the propagation of faults in combinational circuits, the countermeasure guarantees detection of any faulty computation caused by up to t single-bit faults.In this work, we present an experimental analysis of the Impeccable Circuits countermeasure and its underlying assumptions in modern semiconductor technology. More precisely, we have taken hardware implementations of the lightweight block cipher SKINNY equipped with various forms of the EDC-based CED schemes and realized them as cryptographic co-processors on a 40nm ASIC to experimentally evaluate their resistance to Laser Fault Injection (LFI) attacks. In short, our results show that it is fairly simple to overcome the protection offered by the integrated countermeasures when the length of the code n is smaller than twice its rank k (i.e., no full redundancy). This is not caused by any flaw in the underlying design methodology or concept, but merely demonstrates how easily the defined adversary model can be overcome. In our case, a standard black-box scan over the target using a common single-shot LFI setup is sufficient to occasionally inject more single-bit faults than those bounded by the underlying adversary model when n < 2k. The probability of such events proved to be large enough to perform successful key-recovery attacks via Differential Fault Analysis (DFA) in a matter of hours. Thus, we caution against limiting the redundancy in code-based FI countermeasures to less than the number of bits per word, especially in nanometer technologies, and point out that less-complex countermeasures like duplication showed a higher level of resistance in our experiments at a lower cost.

Half diagonal matrix codes for reliable embedded memories

Reliability of embedded memories is dependent on at-speed rated correction capability of error detection and correction codes. Many critical applications like medical databases, rocket launch details stored in memories require accurate data and which cause major human losses or economy losses even if a 1% of data is compromised. This paper focuses on developing improved reliable error detection and correction codes with minimum redundant bits and maximum code rate. The decoder uses the concept of Encoder Reuse Technique along with the Modulo-2 addition to calculate syndrome, error location and correction of data bits when data is read from memory. The codes are represented in verilog hardware description language and simulated in the Tool Xilinx ISE 14.5 for XC7Z020-1CLG484 FPGA. The codes are evaluated for their performance in terms of technology parameters like area, delay, power, power – delay product, etc. Also for other parameters like bit overhead, code rate, code efficiency, correction coverage, correction efficiency, etc and correction coverage per cost for combined evaluation. The implemented half diagonal code is more effective as compared to existing matrix codes, it reduces bit overhead at least by 5.5% to 46.96% and coding rate increased at least by 16.74% to 23.85%.

High-fidelity magic-state preparation with a biased-noise architecture

Magic state distillation is a resource intensive subroutine that consumes noisy input states to produce high-fidelity resource states that are used to perform logical operations in practical quantum-computing architectures. The resource cost of magic state distillation can be reduced by improving the fidelity of the raw input states. To this end, we propose an initialization protocol that offers a quadratic improvement in the error rate of the input magic states in architectures with biased noise. This is achieved by preparing an error-detecting code which detects the dominant errors that occur during state preparation. We obtain this advantage by exploiting the native gate operations of an underlying qubit architecture that experiences biases in its noise profile. We perform simulations to analyze the performance of our protocol with the XZZX surface code. Even at modest physical parameters with a two-qubit gate error rate of $0.7\%$ and total probability of dominant errors in the gate $O(10^3)$ larger compared to that of non-dominant errors, we find that our preparation scheme delivers magic states with logical error rate $O(10^{-8})$ after a single round of the standard 15-to-1 distillation protocol; two orders of magnitude lower than using conventional state preparation. Our approach therefore promises considerable savings in overheads with near-term technology.

MLFTCache: Multilevel Fault Tolerance Scheme for Write-Back L2 Cache Under Irradiation

Cache is prone to soft errors under irradiation, and the incidence rate of multi-bit soft errors in cache memory are becoming larger for modern embedded systems. To improve the cache reliability, we propose a multi-level fault tolerance scheme for write-back L2 cache (MLFTCache). In the workflow of MLFTCache, data bits of cache clean line and dirty line are processed separately. For clean line data bits, 2-way interleaved parity is adopted, and the error is detected and recovered from the next level of memory. For dirty line data bits, the processing is further divided into two layers. The first layer adopts single error correction double error detection (SECDED) code, and the second layer uses multi-bit low redundancy error control with parity sharing (MLREPS) code to detect and correct errors. To reduce the overhead and improve the efficiency of fault tolerance on dirty lines, we adopt two write-back mechanisms. Early write-back mechanism is used to reduce the occurrence of temporal multi-bit soft errors, and emergency write-back mechanism is adopted to deal with the soft error after it is detected. The alpha radiation experiments of Xilinx Zynq-7010 SoC show that cache is prone to multi-bit upsets and the MLFTCache is also dedicated to solving the problem of multi-bit upsets. The cache fault injection and tolerance experiments show that the fault tolerance rate of the MLFTCache proposed in this paper exceeds 90%, while the benchmark schemes are less than 50%. Besides, MLFTCache also has a good performance on dual-core CPU, and its fault tolerance rate on average is 91.34%.

Thirty-six Entangled Officers of Euler: Quantum Solution to a Classically Impossible Problem.

The negative solution to the famous problem of 36 officers of Euler implies that there are no two orthogonal Latin squares of order six. We show that the problem has a solution, provided the officers are entangled, and construct orthogonal quantum Latin squares of this size. As a consequence, we find an example of the long-elusive Absolutely Maximally Entangled state AME(4,6) of four subsystems with six levels each, equivalently a 2-unitary matrix of size 36, which maximizes the entangling power among all bipartite unitary gates of this dimension, or a perfect tensor with four indices, each running from one to six. This special state deserves the appellation golden AME state, as the golden ratio appears prominently in its elements. This result allows us to construct a pure nonadditive quhex quantum error detection code ((3,6,2))_{6}, which saturates the Singleton bound and allows one to encode a six-level state into a triplet of such states.

App-Based Saccade Latency and Directional Error Determination Across the Adult Age Spectrum.

We aid in neurocognitive monitoring outside the hospital environment by enabling app-based measurements of visual reaction time (saccade latency) and directional error rate in a cohort of subjects spanning the adult age spectrum. We developed an iOS app to record subjects with the frontal camera during pro- and anti-saccade tasks. We further developed automated algorithms for measuring saccade latency and directional error rate that take into account the possibility that it might not always be possible to determine the eye movement from app-based recordings. To measure saccade latency on a tablet, we ensured that the absolute timing error between on-screen task presentation and the camera recording is within 5 ms. We collected over 235,000 eye movements in 80 subjects ranging in age from 20 to 92 years, with 96% of recorded eye movements either declared good or directional errors. Our error detection code achieved a sensitivity of 0.97 and a specificity of 0.97. Confirming prior reports, we observed a positive correlation between saccade latency and age while the relationship between directional error rate and age was not significant. Finally, we observed significant intra- and inter-subject variations in saccade latency and directional error rate distributions, which highlights the importance of individualized tracking of these visual digital biomarkers. Our system and algorithms allow ubiquitous tracking of saccade latency and directional error rate, which opens up the possibility of quantifying patient state on a finer timescale in a broader population than previously possible.

Multiple Error Correction in Redundant Residue Number Systems: A Modified Modular Projection Method with Maximum Likelihood Decoding

Error detection and correction codes based on redundant residue number systems are powerful tools to control and correct arithmetic processing and data transmission errors. Decoding the magnitude and location of a multiple error is a complex computational problem: it requires verifying a huge number of different possible combinations of erroneous residual digit positions in the error localization stage. This paper proposes a modified correcting method based on calculating the approximate weighted characteristics of modular projections. The new procedure for correcting errors and restoring numbers in a weighted number system involves the Chinese Remainder Theorem with fractions. This approach calculates the rank of each modular projection efficiently. The ranks are used to calculate the Hamming distances. The new method speeds up the procedure for correcting multiple errors and restoring numbers in weighted form by an average of 18% compared to state-of-the-art analogs.

Logical-qubit operations in an error-detecting surface code

Future fault-tolerant quantum computers will require storing and processing quantum data in logical qubits. Here we realize a suite of logical operations on a distance-2 surface code qubit built from seven physical qubits and stabilized using repeated error-detection cycles. Logical operations include initialization into arbitrary states, measurement in the cardinal bases of the Bloch sphere and a universal set of single-qubit gates. For each type of operation, we observe higher performance for fault-tolerant variants over non-fault-tolerant variants, and quantify the difference. In particular, we demonstrate process tomography of logical gates, using the notion of a logical Pauli transfer matrix. This integration of high-fidelity logical operations with a scalable scheme for repeated stabilization is a milestone on the road to quantum error correction with higher-distance superconducting surface codes.

Detection of Limited Magnitude Errors in Emerging Multilevel Cell Memories by One-Bit Parity (OBP) or Two-Bit Parity (TBP)

Emerging memory technologies rely on Multilevel Cells (MLC) to achieve high density; the use of multiple levels per cell allows storage of multiple bits, but it also reduces the margins and makes it error prone. Error control codes (including error correction and detection codes) can be used to protect MLC memories from errors; however, most existing coding schemes have been designed for traditional binary memories (so storing a single bit). In MLC memories, errors cause a change from a level to an adjacent level or to the next one (depending on the employed technology), so they are often referred to as limited magnitude errors. For a binary coding of levels to bits, these limited magnitude errors can corrupt several bits making traditional coding schemes inefficient. In this paper, error detection of MLC memories is considered when a binary encoding of levels to bits is used and two new schemes are proposed: One-Bit Parity (OBP) and Two-Bit Parity (TBP). The first scheme targets errors of magnitude-1 for detection using a single parity bit that checks only one bit per cell. The second scheme detects both magnitude-1 and -2 errors using only two parity bits. Both schemes are compared to existing alternatives, namely Gray coding combined with a single parity bit (GP) for OBP and Interleaved Parity (IP) for TBP. The results show that OBP reduces the encoding and error detection circuitry complexity and delay, while TBP additionally reduces the number of parity bits for some configurations. Therefore, OBP and TBP can be efficient alternatives for detection of limited magnitude errors in MLC memories that use a binary encoding of levels to bits.

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

Power Series Representation Op logical Functions and its Applications to Error Detection and Error Correction Codes.(Dept.E)

The need for high speed digital storage/retrieval and digital communication systems with error detection and error correction capabilities raises a significant problem to the implementation of error control encoding and decoding. Traditional inplementation has been accomplished through the use of feedback shift register networks. These networks, although being convenient to implement represent a slow process in the overall system since they involve the shifting of code words to generate the error control bits/syndrome. Parallel implementation provides a fast solution, however, it poses a significant complexity to the encoder/decoder implementation. This paper introduces a new implementation for a fast encoder/decoder using analog neural networks. With neural nets as the basic building blocks, the error contra bits/syndrome are asynchronously generated using Op Amps and resistor elements. The problem of fan-in and fan-out inherent in digital implementation is also avoided.