Error Correction Performance Research Articles

Continuous theta burst stimulation over the left pre-motor cortex affects sensorimotor timing accuracy and supraliminal error correction

Adjustments to movement in response to changes in our surroundings are common in everyday behavior. Previous research has suggested that the left pre-motor cortex (PMC) is specialized for the temporal control of movement and may play a role in temporal error correction. The aim of this study was to determine the role of the left PMC in sensorimotor timing and error correction using theta burst transcranial magnetic stimulation (TBS). In Experiment 1, subjects performed a sensorimotor synchronization task (SMS) with the left and the right hand before and after either continuous or intermittent TBS (cTBS or iTBS). Timing accuracy was assessed during synchronized finger tapping with a regular auditory pacing stimulus. Responses following perceivable local timing shifts in the pacing stimulus (phase shifts) were used to measure error correction. Suppression of the left PMC using cTBS decreased timing accuracy because subjects tapped further away from the pacing tones and tapping variability increased. In addition, error correction responses returned to baseline tap–tone asynchrony levels faster following negative shifts and no overcorrection occurred following positive shifts after cTBS. However, facilitation of the left PMC using iTBS did not affect timing accuracy or error correction performance. Experiment 2 revealed that error correction performance may change with practice, independent of TBS. These findings provide evidence for a role of the left PMC in both sensorimotor timing and error correction in both hands. We propose that the left PMC may be involved in voluntarily controlled phase correction responses to perceivable timing shifts.

Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes

Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the Min-max NB-LDPC decoding algorithm. The proposed scheme first sorts out a limited number of the most reliable variable-to-check (v-to-c) messages, then the check-to-variable (c-to-v) messages to all connected variable nodes are derived independently from the sorted messages without noticeable performance loss. Compared to the previous iterative forward-backward check node processing, the proposed scheme not only significantly reduced the computation complexity, but eliminated the memory required for storing the intermediate messages generated from the forward and backward processes. Inspired by this novel c-to-v message computation method, we propose to store the most reliable v-to-c messages as “compressed” c-to-v messages. The c-to-v messages will be recovered from the compressed format when needed. Accordingly, the memory requirement of the overall decoder can be substantially reduced. Compared to the previous Min-max decoder architecture, the proposed design for a (837, 726) code over <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GF</i> (2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ) can achieve the same throughput with only 46% of the area.

Decoding of the (31, 16, 7) quadratic residue code with four-error correcting capability

A high-speed algorithm for decoding the binary (31, 16, 7) quadratic residue (QR) code up to four errors is proposed. Core to the key idea lies in an innovative integration of the reliability-search procedure and the insight of the weight distribution of the code for searching the candidate codewords. Accordingly, the maximum-likelihood (ML) criterion is applied to pick the most possible codeword. Through simulation over the additive white Gaussian noise (AWGN) channel, it is concluded that the error-correcting performance of the new decoder is superior to that of a Chase-II decoder when no more than four errors occur. The overall bit error rate (BER) of the proposed decoder is close to that of the Chase-II decoder. More importantly, the new decoder results in great reductions of 72.34% and 92.37% in the signal-to-noise ratio (SNR) values of 0 and 7, respectively. The proposed algorithm suggests an alternative to enhance the error-correcting capability of the hard-decision decoder, but with a lower decoding complexity.

A Min-Sum Algorithm Suitable for Hardware Implementation Based on LDPC Codes

Decoding algorithms with strong practical value not only have good decoding performance, but also have the computation complexity as low as possible. For this purpose, the paper points out the modified min-sum decoding algorithm(M-MSA). On the condition of no increasing in the decoding complexity, it makes the error-correcting performance improved by adding the appropriate scaling factor based on the min-sum algorithm(MSA), and it is very suitable for hardware implementation. Simulation results show that this algorithm has good BER performance, low complexity and low hardware resource utilization, and it would be well applied in the future.

Construction and Hardware-Efficient Decoding of Raptor Codes

Raptor codes are a class of concatenated codes composed of a fixed-rate precode and a Luby-transform (LT) code that can be used as rateless error-correcting codes over communication channels. These codes have the atypical features of dynamic code-rate, highly irregular Tanner graph check-degree distribution, random LT-code structure, and LT-precode concatenation, which render a hardware-efficient decoder implementation achieving good error-correcting performance a challenging task. In this paper, the design of hardware-efficient Raptor decoders with good performance is addressed through joint optimizations targeting 1) the code construction, 2) decoding schedule, and 3) decoder architecture. First, random encoding is decoupled by developing a two-stage LT-code construction scheme that embeds structural features in the LT-graph that are amenable to efficient implementation while guaranteeing good performance. An LT-aware LDPC precode construction methodology that ensures architectural-compatibility with the structured LT code is also proposed. Second, a decoding schedule is optimized to reduce memory cost and account for processing workload-variability caused by the varying code rate. Third, to address the problems of check-degree irregularity and hardware underutilization, a novel reconfigurable check unit that attains a constant throughput while processing a varying number of LT and LDPC nodes is presented. These design steps collectively are employed to generate serial and partially-parallel decoder architectures. A Raptor code instance constructed using the proposed method having LT data-block length of 1210 is shown to outperform or closely match the performance of conventional LDPC codes over the code-rate range [0.4,2/3]. The corresponding hardware serial decoder is synthesized using 65-nm CMOS technology and achieves a throughput of 22 Mb/s at rate 0.4 for a BER of 10-6, dissipates an average power of 222 mW at 1.2 V, and occupies an area of 1.77mm2.

Performance Analysis of Systematic Upper Layer FEC Codes and Interleaving in Land Mobile Satellite Channels

This paper provides an analytical method for evaluating the performance of upper layer forward error correction (FEC), when used together with interleaving on land mobile satellite channels, in terms of residual (after decoding) packet loss rate (PLR). In addition, the analysis highlights the overheads introduced by this technique, which depend on the channel statistics, in terms of additional packet delivery delay, bandwidth consumption, and computation power required. We show why the interleaver is mandatory in some environments, due to the severe disruptive characteristics of the channel, according to measurement campaigns promoted by the European Space Agency. This analysis provides the expression of the residual PLR when systematic FEC coding blocks are interleaved at the packet level (i.e., when a cyclic redundancy check and a sequence number identify a correct data unit). This method can be employed for the performance evaluation of recent and future mobile communication systems that take advantage of upper layer FEC and interleaving techniques.

From metalinguistic instruction to metalinguistic knowledge, and from metalinguistic knowledge to performance in error correction and oral production tasks

The purpose of this study is to analyse the effect of metalinguistic instruction on students’ metalinguistic knowledge on the one hand, and on students’ performance in metalinguistic and oral production tasks on the other hand. Two groups of primary school students learning English as a foreign language were chosen. One of them (Rule group) was provided with metalinguistic instruction on English possessive determiners (PDs) for six weeks (N= 21), while the Comparison group (N= 22) did not receive such instruction. These students’ progress was analysed through a pre-test/post-test design by means of a written error correction task, a ‘free production’ oral task, and a metalinguistic judgement task. The results of the statistical analyses indicate that, although the learners in the Rule group were more advanced in their knowledge and use of the English PDs than their peers in the Comparison group, the differences between groups were not statistically significant in all the tests. Additional analyses revealed that there were correlations between students’ knowledge and performance in the Rule group, indicating that the learners who made the most gains from pre- to post-test were the ones who had demonstrated a more advanced knowledge of the rule.

Fixed-Point MAP Decoding of Channel Codes

This paper describes the fixed-point model of the maximum a posteriori (MAP) decoding algorithm of turbo and low-density parity-check (LDPC) codes, the most advanced channel codes adopted by modern communication systems for forward error correction (FEC). Fixed-point models of the decoding algorithms are developed in a unified framework based on the use of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. This approach aims at bridging the gap toward the design of a universal, multistandard decoder of channel codes, capable of supporting the two classes of codes and having reduced requirements in terms of silicon area and power consumption and so suitable to mobile applications. The developed models allow the identification of key parameters such as dynamic range and number of bits, whose impact on the error correction performance of the algorithm is of pivotal importance for the definition of the architectural tradeoffs between complexity and performance. This is done by taking the turbo and LDPC codes of two recent communication standards such asWiMAX and 3GPP-LTE as a reference benchmark for a mobile scenario and by analyzing their performance over additive white Gaussian noise (AWGN) channel for different values of the fixed-point parameters.

Minimal-memory realization of pearl-necklace encoders of general quantum convolutional codes

Quantum convolutional codes, like their classical counterparts, promise to offer higher error correction performance than block codes of equivalent encoding complexity, and are expected to find important applications in reliable quantum communication where a continuous stream of qubits is transmitted. Grassl and Roetteler devised an algorithm to encode a quantum convolutional code with a "pearl-necklace encoder." Despite their theoretical significance as a neat way of representing quantum convolutional codes, they are not well-suited to practical realization. In fact, there is no straightforward way to implement any given pearl-necklace structure. This paper closes the gap between theoretical representation and practical implementation. In our previous work, we presented an efficient algorithm for finding a minimal-memory realization of a pearl-necklace encoder for Calderbank-Shor-Steane (CSS) convolutional codes. This work extends our previous work and presents an algorithm for turning a pearl-necklace encoder for a general (non-CSS) quantum convolutional code into a realizable quantum convolutional encoder. We show that a minimal-memory realization depends on the commutativity relations between the gate strings in the pearl-necklace encoder. We find a realization by means of a weighted graph which details the non-commutative paths through the pearl-necklace. The weight of the longest path in this graph is equal to the minimal amount of memory needed to implement the encoder. The algorithm has a polynomial-time complexity in the number of gate strings in the pearl-necklace encoder.

On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory

As technology continues to scale down, NAND Flash memory has been increasingly relying on error-correction codes (ECCs) to ensure the overall data storage integrity. Although advanced ECCs such as low-density parity-check (LDPC) codes can provide significantly stronger error-correction capability over BCH codes being used in current practice, their decoding requires soft-decision log-likelihood ratio (LLR) information. This results in two critical issues. First, accurate calculation of LLR demands fine-grained memory-cell sensing, which nevertheless tends to incur implementation overhead and access latency penalty. Hence, it is critical to minimize the fine-grained memory sensing precision. Second, accurate calculation of LLR also demands the availability of a memory-cell threshold-voltage distribution model. As the major source for memory-cell threshold-voltage distribution distortion, cell-to-cell interference must be carefully incorporated into the model. However, these two critical issues have not been ever addressed in the open literature. This paper attempts to address these open issues. We derive mathematical formulations to approximately model the threshold-voltage distribution of memory cells in the presence of cell-to-cell interference, based on which the calculation of LLRs is mathematically formulated. This paper also proposes a nonuniform memory sensing strategy to reduce the memory sensing precision and, thus, sensing latency while still maintaining good error-correction performance. In addition, we investigate these design issues under the scenario when we can also sense interfering cells and hence explicitly estimate cell-to-cell interference strength. We carry out extensive computer simulations to demonstrate the effectiveness and involved tradeoffs, assuming the use of LDPC codes in 2-bits/cell NAND Flash memory.

Implementation and performance of parallellised turbo decoders

In this study, the authors discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, resource consumption, error correction performance and the data (information bit) rate. In order to decrease the latency a parallellised decoder structure is introduced for these mentioned codes and the results are obtained by implementing the decoders on a field programmable gate array. The memory collision problem is avoided by using collision-free interleavers. Through a proposed quantisation scheme and normalisation in forward/backward recursions, computational issues are handled for overcoming the overflow and underflow issues in a fixed point arithmetic. Also, the effect of different implementation styles are observed.

Adaptive buffer control to minimise delay and guarantee service reliability

Delay-sensitive real-time applications require average latency to be reduced as far as possible, while maintaining the minimum necessary level of service quality. However, the interaction of these two performance metrics has not received much attention in the current standard air specification of CDMA2000 broadcast services. The authors analyse the performance of the forward error correction employed at the MAC layer of these broadcast services, with respect to the conditions of a fading wireless channel and the size of the error control block (ECB), which is a buffer in the form of a two-dimensional array. As a result, the authors establish the tradeoff between service reliability and delay, and show how it depends on the size of the ECB. The authors go on to propose a novel adaptive error-recovery scheme which dynamically adjusts the size of the ECB to suit the wireless environment of the mobile nodes, using either a moving-average or a weighted-average method. Reducing the service delay as far as possible necessarily compromises the reliability of the service, but the authors scheme still ensures the required minimum reliability. The authors have shown the effectiveness of their scheme through extensive simulations using a detailed threshold model, which accurately describes the statistics of the block error process in a fading channel. The authors also suggest a service implementation scenario to aid in the design.

Stochastic Decoding of Turbo Codes

Stochastic computation is a technique in which operations on probabilities are performed on random bit streams. Stochastic decoding of forward error-correction (FEC) codes is inspired by this technique. This paper extends the application of the stochastic decoding approach to the families of convolutional codes and turbo codes. It demonstrates that stochastic computation is a promising solution to improve the data throughput of turbo decoders with very simple implementations. Stochastic fully-parallel turbo decoders are shown to achieve the error correction performance of conventional a posteriori probability (APP) decoders. To our knowledge, this is the first stochastic turbo decoder which decodes a state-of-the-art turbo code. Additionally, an innovative systematic technique is proposed to cope with stochastic additions, responsible for the throughput bottleneck.

A 26.9 K 314.5 Mb/s Soft (32400,32208) BCH Decoder Chip for DVB-S2 System

This paper provides a soft Bose-Chaudhuri-Hochquenghem (BCH) decoder chip with soft information from the LDPC decoder for the DVB-S2 system. In contrast with the hard BCH decoder, the proposed soft BCH decoder that deals with least reliable bits can provide much lower complexity with similar error-correcting performance. Moreover, the error locator evaluator is proposed to evaluate error locations without the Chien search for higher throughput, and the Bjorck-Pereyra error magnitude solver (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The chip measurement results reveal that our proposed soft (32400, 32208) BCH decoder for DVB-S2 system can achieve 314.5 Mb/s with a gate-count of 26.9 K in standard 90 nm 1P9M CMOS technology. Extended for fully supporting 21 modes in the DVB-S2 system, our approach can achieve 300 MHz operation frequency with a gate-count of 32.4 K.

Entanglement-assisted quantum low-density parity-check codes

This paper develops a general method for constructing entanglement-assisted quantum low-density parity-check (LDPC) codes, which is based on combinatorial design theory. Explicit constructions are given for entanglement-assisted quantum error-correcting codes (EAQECCs) with many desirable properties. These properties include the requirement of only one initial entanglement bit, high error correction performance, high rates, and low decoding complexity. The proposed method produces infinitely many new codes with a wide variety of parameters and entanglement requirements. Our framework encompasses various codes including the previously known entanglement-assisted quantum LDPC codes having the best error correction performance and many new codes with better block error rates in simulations over the depolarizing channel. We also determine important parameters of several well-known classes of quantum and classical LDPC codes for previously unsettled cases.

Assessing for generalized improvements in reading comprehension by intervening to improve reading fluency

AbstractThe relationship between reading fluency and comprehension was evaluated in five 4th‐grade students. These students were identified as being at risk of not meeting yearly goals in reading fluency and comprehension based on fall benchmark assessment data. A brief intervention assessment was used to determine which intervention components would be essential to improving reading fluency across the five participants. As a result, the combination of repeated practice with performance feedback and error correction was implemented using instructional‐level reading materials twice per week for 30‐minute sessions with progress monitored weekly using AIMSweb measures of oral reading fluency and comprehension. Empirical, single‐case designs were used to evaluate the impact of the program across these five students with assessed, generalized improvements in comprehension. Results indicated increased rate of words read correctly per minute with generalized increases in comprehension for four of five participants. Implications for practice and directions for future research are discussed. © 2010 Wiley Periodicals, Inc.

Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding

By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density advantage. However, continuous technology scaling makes MLC NAND flash memories increasingly subject to worse raw storage reliability. This paper presents a memory fault tolerance design solution geared to MLC NAND flash memories. The basic idea is to concatenate trellis coded modulation (TCM) with an outer BCH code, which can greatly improve the error correction performance compared with the current design practice that uses BCH codes only. The key is that TCM can well leverage the multi-level storage characteristic to reduce the memory bit error rate and hence relieve the burden of outer BCH code, at no cost of extra redundant memory cells. The superior performance of such concatenated BCH-TCM coding systems for MLC NAND flash memories has been well demonstrated through computer simulations. A modified TCM demodulation approach is further proposed to improve the tolerance to static memory cell defects. We also address the associated practical implementation issues in case of using either single-page or multi-page programming strategy, and demonstrate the silicon implementation efficiency through application-specific integrated circuit design at 65 nm node.

Algebraic Soft-Decision Decoder Architectures for Long Reed–Solomon Codes

Algebraic soft-decision (ASD) decoders of Reed-Solomon (RS) codes can achieve significant coding gain with polynomial complexity. Most prior work on ASD decoder architecture design is for relatively short RS codes. However, one major application of RS codes, magnetic recording, usually requires a code length of 4Kbits or longer. For long RS codes, the low-complexity Chase (LCC) ASD decoding needs to interpolate over a large number of test vectors, which leads to long latency. This brief proposes a unified backward-forward interpolation scheme and a corresponding architecture for the LCC decoding. The proposed architecture can achieve almost twice the speed with only 40% area overhead. Another contribution of this brief is that the hardware complexity analysis for different ASD decoders is provided for the first time. For a (458, 410) RS code over GF(210), the proposed LCC decoder can achieve much higher efficiency in terms of speed-over-area ratio than other ASD decoders with similar error-correcting performance.

MBMS raptor codes design trade-offs for IPTV

Raptor codes bring significant improvement to the performance of the forward error correction (FEC) scheme for 3rd Generation Partnership Program (3GPP) Multimedia Broadcast/Multicast Services (MBMS). They have become an integrated part of the fast growing mobile consumer services and technologies - the multimedia content broadcast and delivery. In this work, we analyze the trade-offs involved in the implementation of systems employing MBMS. We show the performance for various packet erasure rates with fixed and variable Raptor code symbol overhead. We analyze the quality of service, for different block and symbol sizes and system throughputs. With the rise of new highly attractive but computationally intensive services, the lack of either the performance or the power in the mobile devices becomes a serious issue. We investigate the limiting effects of the Raptor decoder complexity on the performance of the mobile receiver system. Finally, we identify the system parameters that trade-off the Raptor coding performance for the decoding complexity.

Sentence Correction Incorporating Relative Position and Parse Template Language Models

Sentence correction has been an important emerging issue in computer-assisted language learning. However, existing techniques based on grammar rules or statistical machine translation are still not robust enough to tackle the common errors in sentences produced by second language learners. In this paper, a relative position language model and a parse template language model are proposed to complement traditional language modeling techniques in addressing this problem. A corpus of erroneous English-Chinese language transfer sentences along with their corrected counterparts is created and manually judged by human annotators. Experimental results show that compared to a state-of-the-art phrase-based statistical machine translation system, the error correction performance of the proposed approach achieves a significant improvement using human evaluation.