Erase State Research Articles

Proton Radiation Effects on Nanocrystal Non-Volatile Memories

We report on proton radiation effects on Si-nanocrystal (Si-NCs) MOS capacitors and nMOS transistors aiming at non-volatile memory applications. Irradiation experiments were conducted on NC MOS capacitors using protons of 1.5 MeV and 6.5 MeV and on NC nMOS transistors using protons of 1.5 MeV. The range of doses investigated was ~ 1 to ~ 100 Mrad (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). A 2-D layer of Si NCs with ~ 3 nm mean diameter and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> surface density was successfully achieved by low-energy (1 keV) ion-beam-synthesis in thin SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layers. After irradiation, programmed capacitors are found to undergo bit flip while programmed transistors are not. Charge retention measurements at room temperature for the write and erase states of irradiated and non-irradiated samples reveal that a significant memory window exists at an extrapolated time of ten years even after an irradiation dose as high as 120 Mrad (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). The flat-band decay rate of the erase state in NC MOS capacitors does not depend on the irradiation-dose while the opposite occurs for the write state which is found to be directly dependent on D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> values after irradiation. These results clearly indicate that NC non-volatile memories (NVM) are promising radiation tolerant devices.

垂直磁気転写された磁化状態のマイクロマグネティックシミュレーション

We demonstrated the micromagnetic simulation of magnetic duplication for perpendicular magnetic recording (PMR) media. The magnetization distributions of the PMR media duplicated by edge printing (EP) and bit printing (BP) were investigated. The dependence of duplication characteristics on the duplication field was also estimated. An AC erase state in the off-track region appeared for a strong duplication field in EP. The dependence of the duplication characteristics on the duplication field we found in this study is in agreement with that calculated by macroscopic-magnetization analysis in a previous report. Although the intergrain exchange constant has almost not influence on the duplication characteristics in EP, the duplication characteristics in BP are improved as the intergrain exchange constant increases.

Proton radiation tolerance of nanocrystal memories

We report on proton radiation tolerance of Si-nanocrystal (Si-NCs) MOS structures aiming at non-volatile memory applications. Si-NCs were formed by low-energy (1 keV) ion-beam-synthesis within a 9 nm thick SiO 2 layer. A 2-D layer of Si-NCs with 3 nm mean diameter and 10 12 cm −2 surface density was successfully achieved. After fabrication of Al capacitors, samples with and without Si-NCs were 1.5 and 6.5 MeV proton were irradiated at doses ranging from 1 Mrad (SiO 2) to 120 Mrad (SiO 2). Significant irradiation-dose-dependent shifts are detected in the C– V curves of the NC-MOS cells and programmed cells are found to undergo bit flip. Despite the above, the attainable memory windows after write/erase operations remain unchanged. Retention time characteristics at room temperature for the write and erase states of irradiated and non-irradiated samples reveal that even after an irradiation dose as high as 120 Mrad (SiO 2) the devices still exhibit long time charge storage behavior. We observe that the erase state flat-band voltage decay rate does not depend on the irradiation-dose while the opposite happens for the write state flat-band voltage decay rate which is found to be directly dependent on D it values giving insight to the physics of the discharging mechanisms.

0.25 μm 표준 CMOS 로직 공정을 이용한 Single Polysilicon EEPROM 셀 및 고전압소자

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a <TEX>$0.25{\mu}m$</TEX> standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

Impact of metal work function on memory properties of charge-trap flash memory devices using fowler-nordheim P/E mode

This letter reports the impact of metal work function (/spl Phi//sub M/) on memory properties of charge-trap-Flash memory devices using Fowler-Nordheim program/erase mode. For eliminating electron back tunneling and hole back tunneling through the blocking oxide during an program/erase operation, a gate with /spl Phi//sub M/ of 5.1-5.7 eV on an Al/sub 2/O/sub 3/-SiN-SiO/sub 2/ (ANO) stack is necessary. Compared to a thickness optimized n/sup +/ poly-Si/ONO stack, a high-work-function gate on an ANO stack shows dramatic improvements in retention versus minimum erase state.

High-performance single polysilicon EEPROM with stacked MIM capacitor

High-performance single polysilicon electrically erasable programmable read-only memories (EEPROMs) with stacked metal-insulator-metal capacitor as a control gate are investigated. The thickness of the tunnel oxide and the length of the floating gate channel of the fabricated devices were 52 /spl Aring/ and 0.24 /spl mu/m, respectively. The effective control gate coupling ratio of the proposed EEPROM cell was higher than that of cells with n-well control gate because of the absence of depletion capacitance in the n-well silicon region. The experimental results showed that the program speed of the proposed cells were faster than those of the conventional n-well control gate cells. In addition, the proposed cells had threshold voltage shifts of 3.5 V between program and erase states. Furthermore, there were threshold voltage shifts of 3.0 V without degradation of the read currents after 1000 program/erase cycles.

The Effect of Fixed Oxide Charge in Al[sub 2]O[sub 3] Blocking Dielectric on Memory Properties of Charge Trap Flash Memory Devices

In this article, we report the effect of fixed oxide charge in Al 2 O 3 blocking dielectric on memory properties of charge trap flash memory devices using Fowler-Nordheim program/erase mode. It was found that negative fixed oxide charges in the Al 2 O 3 dielectric play a crucial role in improving erase efficiency of Al 2 O 3 /SiN/SiO 2 (ANO) stacks, and thus reinforces the advantages of a Al 2 O 3 blocking layer for charge trap flash devices. Compared to n + poly-Si/ONO stack, process-optimized ANO stack with high work-function metal gate shows dramatic improvements in retention vs minimum erase state.

Fully compatible novel SNONOS structure for improved electrical performance in NAND Flash memories

A fully integrated gate stack structure with an additional stoichiometric silicon nitride layer in the control oxide referred to as “SNONOS” is used to improve the electrical performance of nitride-based memories. The process is completely compatible with conventional silicon processes. By employing the new structure, the detrimental “back-tunneling” effect is suppressed without sacrificing device capacitance. Thus, a threshold voltage improvement of approximately 1.2 V is observed for the erase state. Retention for devices with similar erase performance is also improved with the SNONOS structure. Further mitigation of the “back-tunneling” effect is observed for devices with high work function gate material.

Lateral Migration of Trapped Holes in a Nitride Storage Flash Memory Cell and Its Qualification Methodology

The negative threshold voltage (V/sub t/) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this V/sub t/ shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced V/sub t/ shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative V/sub t/ drift is proposed.

Write/Erase Cycling Endurance of Memory Cells With SiO&amp;lt;tex&amp;gt;$_2$&amp;lt;/tex&amp;gt;/HfO&amp;lt;tex&amp;gt;$_2$&amp;lt;/tex&amp;gt;Tunnel Dielectric

The write/erase cycling endurance of low voltage floating-gate memory cells programmed and erased by tunneling through a SiO/sub 2//HfO/sub 2/ dual layer tunnel dielectric stack is investigated. The use of fixed single pulse program and erase conditions leads to fast shifting (after /spl sim/1000 cycles) of the threshold voltage window, so that only a limited number of write/erase cycles can be achieved. Increasing the write and erase duration quickly leads to an excessive erase time so that a different erase method has to be used. Improvement of the erase behavior and cycling endurance has been obtained by a combination of two methods. Inclusion of soft write pulses between the erase pulses reduces the amount of charge trapped in the tunnel dielectric and therefore limits the increase in erase time. Also, the erase voltage can progressively be raised in order to further limit the erase time, leading to an endurance of 10 000 cycles on the considered cells. When combining the SiO/sub 2//HfO/sub 2/ stack with channel hot electron injection so that tunneling is only required in one direction, 100 000 write/erase cycles are demonstrated with minimal change of the memory window.

An endurance evaluation method for flash EEPROM

Trap generation is hard to estimate in a Flash cell due to a dynamic stress field during program and erase. In this paper, a linear correlation is found between the erase state V/sub T/ rollup and cycling V/sub T/ window. With the knowledge of the time dependence of erase stress field based on Fowler-Nordheim (FN) tunneling, the V/sub T/ rollup during cycling is evaluated by incorporating field dependent oxide trap generation. The extracted /spl Delta/V/sub T/ degradation slope during constant FN stress can be applied quantitatively to predict the V/sub T/ window closure during Flash cell cycling.

Spatial characterization of localized charge trapping and charge redistribution in the NROM device

This paper discusses the spatial characterization and redistribution of hot carriers injected into the gate dielectric stack of the NROM localized charge trapping non-volatile memory device. The spatial characterization is based on a novel experimental method, which combines subthreshold and gate-induced-drain-leakage current measurements with two-dimensional drift diffusion simulations. It is shown that electron and hole trapping takes place in a narrow region near the drain junction, with a ∼20 nm tail situated above the transistor channel. The ability to adjust the hole injection location was demonstrated by characterizing trapped hole distributions following erasure under two different bias conditions. The NROM cell erase state threshold voltage drift is spatially quantified and shown to be a manifestation of lateral charge redistribution originating from the mismatch between the trapped electron and hole distributions inside the gate dielectric stack. The charge localization concept is shown to allow NROM technology to achieve both excellent scalability and high reliability.

Lateral charge transport in the nitride layer of the NROM non-volatile memory device

NROM is a two bits per cell, localized charge trapping non-volatile memory device. A unique erase state threshold voltage drift in the NROM cell is presented. The research aimed to determine the origin of this phenomenon and assess the role of lateral misalignment between electrons and holes trapped in the ONO gate dielectric stack. Electrical characterizations combined with two-dimensional drift diffusion simulations and charge-tunneling theory were employed. It was found that the drift direction could be controlled by alteration of the voltages applied to the cell during erasure. Furthermore, the drift diminished with the number of program/erase cycles performed on the cell and demonstrated an insensitivity to vertical electric fields applied to the device. A lateral trap-to-trap hole-tunneling model was developed and shown to resolve the unique drift characteristics. Theories ascribing vertical charge tunneling to this phenomenon are demonstrated as inconsistent with most of these observations.

20-Mb/s erase/record flash memory by asymmetrical operation

An asymmetrical recording and erasing operation of Flash memory is proposed where the threshold voltage of erase and record states are set above the thermal equilibrium threshold voltage. The recording rate is made ten times faster by using this method along with two other proposed methods: accurate control of the fastest bit and continuous recording using two memory banks. The erasing rate is also made ten times faster by using large-scale parallel operation made practical by a proposed multiphase word-driving scheme. These proposed circuit technologies will enable 20-Mb/s erase/record Flash memories for use in personal high-definition television (HDTV) movie cameras.

Self-Sharpening Effect of Phase Change Erasable Media

The characteristics of single-beam one-pass overwrite of SbTeGe phase change erasable (PCE) optical disks have been studied from a drive design point of view. In the recording process, an amorphous mark surrounded by a crystal ring (erase state) is recorded.The amorphous mark always has a clear edge even if erasability is relatively low in the low erase power area. We call this phenomenon the self-sharpening effect (SSE) which gives several advantages to the performance and design of the drive. SSE realizes wide power tolerance in a practical drive, which results in excellent interchangeability in terms of write/erase laser power. SSE also achieves a good off-track performance of less than +/- 0.1 µm of the optical beam and enables pulse edge recording even if overwrite erasability is relatively low.