Erase Efficiency Research Articles

String-level compact modeling of erase operations in the body-floated vertical channel of 3D charge trapping flash memory

In this study, we examined the use of string-level compact modeling as an effective framework for circuit simulation focusing on erase operation in 3D charge trapping flash (CTF) memory devices. We analyzed the behaviors of the accumulated hole from p-type bulk (p-well) and the corresponding difference of channel electrostatic potential in the CTF cell string, which is attributed to the variation in hole barrier height in the channel of the ground select line (GSL) transistor during erase operation. We derived a formula for the hole current delivering positive potential from the p-well to the channel region and established a modeling procedure. Technology computer-aided design (TCAD) simulation results were used to extract model parameters and analyze channel electrostatic potential during the erase operation. Additionally, experimental data for erase speed were verified using simulation program with integrated circuit emphasis (SPICE) results. Because the erase efficiency is strongly related to hole behaviors based on the conditions of the GSL transistor, the proposed compact modeling is an effective tool for circuit designers and system architects to achieve better performance in erase execution and optimizing the design of 3D CTF memory devices.

Damage and optimization of program/erase operation in MANOS 3D NAND flash memory

In this work, the damage caused by program/erase (P/E) operation in 3D NAND memory devices made of Metal-Al2O3-Nitride-Oxide-Semiconductor (MANOS) was examined. The damage caused by program and erase operations independently was intended to be identified and realized using several types of cycling stresses. Physical models were discussed to interpret that the anode hole could be responsible for the damage to the Al2O3-Nitride-Oxide (ANO) gate stacks. The tunnel oxide damage was caused by the erase operation and could be enhanced by a higher cycling temperature. This led to a faster program and a slower erase, and it demonstrated a strong correlation with retention and its active energy (Ea). On the other hand, program operation may merely be contributing to block oxide damage, with an invisible impact on erase efficiency and retention but a reduction in program efficiency. An optimized single pulse erase scheme was discussed. Not only can it reduce ANO damage and improve retention, but it can also decrease erase time. Furthermore, a feasible endurance acceleration method was discussed to save a lot of cycling time.

Erase Speed Enhancement with Low Power Operation by Incorporating Boron Doping

In this paper, it is shown that the erase efficiency of the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type nonvolatile charge trapping memory (CTM) is greatly improved by adjusting boron doping. Tunnel FET (TFET) based SONOS memory, which has p-type at source side, is superior to MOSFET based SONOS memory in terms of hole supplement and erase speed. In order to discover the specific physical reasons of this erase speed enhancement, MOSFET based SONOS memory devices with different body doping concentration are additionally investigated. As a result, it is found that the more hole supplement from source side in TFET and body side in MOSFET accelerates the erase speed and erase speed enhancement can be realized by utilizing boron doping. Furthermore, erase speed depending on device geometry, in terms of source-to-gate overlap length and gate length, is also analyzed. Interestingly, it is demonstrated that source overlap technique, which has been implemented for suppression of ambipolar current, is also possible to accelerate erase speed.

Analysis of a Schottky Barrier MOSFET for Synaptic Device Using Hot Carrier Injection

In this paper, we analyze the hot carrier injection (HCI) in an asymmetric dual-gate structure with a metallic source/drain. We propose a program/erase scheme where HCI occurs on the source side of the body. Owing to the large resistance of the Schottky barrier used, a large electric field is formed around the Schottky barrier. Therefore, impact ionization occurs as the gate voltage is increased and hot carriers are injected into the source side, which is less influenced by the drain voltage. We also analyze the program and erase efficiency by adjusting the Schottky barrier height or by using dopant segregation technique. We expect a small amount of current to flow and great efficiency of the program/erase operations to use as a synaptic device.

A Novel Structure for Improving Erase Performance of Vertical Channel NAND Flash With an Indium-Gallium-Zinc-Oxide Channel

We propose a novel structure to solve the hole erase problem of Indium-Gallium-Zinc-Oxide (IGZO) channels. The proposed structures are an IGZO-nitride-P filler (INP) structure and an IGZO-P filler (IP) structure. In the simulations using both structures, stable operation and erase efficiency can be achieved in an INP structure when the nitride barrier thickness is 7 nm. The erase performance achieved exceeds that of the polysilicon channel under the same conditions. Conversely, if the nitride thickness exceeds 8 nm, the read operation becomes unstable. Therefore, nitride thickness is an important parameter in the operation of an INP structure, and its maximum value is 7 nm. For improving upon this INP structure, the nitride was removed to create an IP structure, in which, leakage currents could be limited by reducing doping concentration. In particular, such an IP structure showed that the maximum erase performance (2 ms) of the polysilicon channel can only be achieved at $2.3~\mu \text{s}$ , and then the erase operation can continue. This result is due to lack of electron accumulation in the channel and their ability to move quickly through the filler directly connected to the IGZO channel. As a result, both proposed structures have shown that low erase performance can be overcome without sacrificing the excellent leakage current blocking characteristics of IGZO material.

Electrochemical, photovoltaic and DFT studies on hybrid materials based on supramolecular self-assembly of a ditopic twisted perylene diimide with square-planar platinum(II)- and/or palladium(II)-2,2′:6′,2″-terpyridyl complex ions

A ditopic bridging ligand, N,N′-bis(pyridine)-1,6,7,12-tetrakis-(4-methoxyphenoxy)perylene diimide (1) was synthesized. Metallosupramolecular self-assembly of 1 with 2,2′:6′,2″-terpyridyl-platinum(II) and/or -palladium(II) complex ions afforded to new triads [(terpy)M(II)-(1)-M(II)(terpy)](NO3)4 where, M(II) = Pt(II) (2), and Pd(II) (3), respectively. These isolated triads 2 and 3 and also free ligand 1 were fully characterized by FT-IR, 1H NMR, 13C DEPT NMR, 1H-1H COSY NMR, MALDI TOF and HRMS (MALDI-TOF/TOF-MS) mass techniques and UV/Vis spectroscopy. DFT studies revealed that the molecular structure of 1 is highly distorted and deviated from the planarity by bulky methoxyphenyl groups at bay positions. The calculated HOMO and LUMO are located on the PDI core and phenyl groups, and the band gap was found to be 2.27, 2.23 and 2.24 eV in DMSO for 1, 2 and 3, respectively. The calculated UV/Vis spectra are in good agreement with those of experimental results. Electrochemical, in situ spectroelectrochemical and in situ electrocolorimetric measurements in solution suggested that redox processes of the compounds are accompanied by favourable electron transport properties with remarkably narrow HOMO-LUMO gaps and intense light absorption over the visible range. The association of usually reversible and fast electron transfer processes with the net colour changes in solution pointed out the applicability of the compounds as an electrochromic material. The electrochromic performance measurements with the films of the compounds on indium tin oxide glass provided additional support for their usability as a colour changing material in electrochromic devices. Surface morphologies of the films were characterized by scanning electron microscopy (SEM). The metal complexes of 1, especially the platinum(II) complex (2), behaved as a good neutral and cathodic colouring electrochromic material with fast response time, long-term stability, and long-term write erase efficiency. The photovoltaic performance of the compounds as electron acceptor material was investigated by varying their relative ratio in the bulk heterojunction solar cells. It was found that the photovoltaic conversion efficiency of the devices strongly depends on the blend ratio. The optimized performance for the devices was obtained with the P3HT:PDIs (weight ratio 1.0:1.5) blended films. For this blend ratio, the device showed a maximum conversion efficiency of 3.91%, 8.17% and 5.18% for 1, 2 and 3, respectively. The results obtained reveal that employing 2 as an acceptor material has great potential for the development of highly efficient nonfullerene bulk heterojunction photovoltaic devices.

An Erase Efficiency Boosting Strategy for 3D Charge Trap NAND Flash

Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory. Among these new techniques, 3D charge trap flash is considered to be one of the most promising candidates for the next-generation NAND flash devices. However, the long erase latency of 3D charge trap flash becomes a critical issue. This issue is exacerbated because the distinct transient voltage shift phenomenon is worsened when the number of program/erase cycle increases. In contrast to existing works that aim to tackle the erase latency issue by reducing the number of block erases, we tackle this issue by utilizing the “multi-block erase” feature. In this work, an erase efficiency boosting strategy is proposed to boost the garbage collection efficiency of 3D charge trap flash via enabling multi-block erase inside flash chips. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the erase efficiency and access performance of 3D charge trap flash. The results show that the erase latency of 3D charge trap flash memory is improved by 75.76 percent on average even when the P/E cycle reaches $10^{4}$ .

Microscopic Analysis of Erase-Induced Degradation in 40 nm NOR Flash Technology

An in-depth investigation of NOR flash degradation occurring during Fowler–Nordheim (FN) erase operation is provided. After showing how to properly reproduce the flash equivalent stress on transistors, a complete set of delay-free experiments is performed on MOSFET devices. This paper explores FN-induced SiO2 damage from the two oxide interfaces, capturing both electrostatic aging, by reading the drifts of linear characteristics on single MOSFET, and erase efficiency degradation of the memory cell, by measuring the gate current evolution directly on array structures. After showing how to read the signatures of different defects, important insights are given on physical degradation mechanisms and significant guidelines are provided for the extraction of relevant physical-based parameters for modeling and optimization of flash cell endurance. In particular, the power law correlation between injected and trapped charges has been observed for both types of carriers, highlighting the difference in the power exponent which leads to a turnaround of Vth at erase state during flash endurance. It has been underlined how the holes are mainly trapped close to Si/SiO2 interface, essentially influencing the electrostatics, whereas the electrons are mainly located close to poly/SiO2 interface, mostly impacting the gate current. In addition, an accurate noise-free extraction of electrostatic parameters related to holes and amphoteric defects has been performed highlighting the negligible shift of the total threshold voltage. Finally, the interface trap aging kinetics has been experimentally addressed, emphasizing the weak electron-energy dependence.

Band-to-Band Hot Hole Erase Mechanism of p-Channel Junctionless Silicon Nanowire Nonvolatile Memory

In this paper, p-channel junctionless (JL) silicon-oxide–nitride-oxide–silicon (SONOS)-type nonvolatile memory (NVM) devices with gate-all-around (GAA) nanowire (NW) structure by using silicon-nanocrystal for the charge-trapping layer are presented. The devices exhibited good erase efficiency and excellent retention behavior and can be used in system-on-panel and 3-D-stacked flash memory applications. In addition, a band-to-band hot hole (BBHH) method for erasing is proposed and compared with the Fowler–Nordheim (FN) tunneling method. Because FN erasing requires a high gate voltage, BBHH erasing, which requires a low voltage, can increase the service life of the memory. Channel hot electron and band-to-band hot electron were used for programming and yielded low programming efficiency for the p-channel JL GAA NW NVM devices because of a lack of electron carriers. The program/erase efficiency is related to the channel type in JL NVM devices.

Nitrogen induced modifications of MANOS memory properties

In this work we examine the structural and electrical properties including the memory performance of Al2O3/Si3N4/SiO2 dielectric stacks implanted with low-energy nitrogen ions and subsequently thermal annealed at 850 or 1050°C for 15min. X-ray photoelectron spectroscopy reveals that the concentration and the chemical state of the nitrogen atoms within the Al2O3 layer depends on the post-implantation annealing (PIA) temperature. Memory testing, performed on platinum gate capacitors, shows that charge retention of the programmed states is significantly improved for the high-temperature PIA samples as compared to the non-implanted samples. While such an improvement is not detected for the low-temperature PIA samples, the latter exhibit enhanced hole charging and thus, increased erase efficiency. Overall, our results suggest that the transport properties which control the erase and the retention characteristics of the blocking Al2O3 layer can be tailored by nitrogen implantation and the PIA conditions and can be used for memory performance optimization.

Enhanced electrochromic write–erase efficiency of a device with a novel viologen: 1,1′-bis(2-(1H-indol-3-yl)ethyl)-4,4′-bipyridinium diperchlorate

A novel cathodically coloring viologen electrochrome: 1,1′-bis(2-(1H-indol-3-yl)ethyl)-4,4′-bipyridinium diperchlorate (IEV), comprising of a 4,4′-bipyridyl core, sandwiched between two indole moieties, was synthesized using 3-(2-bromoethyl)-indole. An electrochromic device (ECD) was assembled using an electrolyte containing an imidazolium imide ionic liquid and characterized by a large electrical conductivity, thermal stability upto 150°C, and an electrochemical potential stability range of ∼3.6V. The IEV viologen was dissolved in the electrolyte and Prussian blue was used as the anodic electrochrome. The indole moieties of the IEV2+ salt owing to their electron donating tendency can act like bleaching agents and bleach the viologen faster (IEV+→IEV2+) and this hypothesis was used for the improved write–erase efficiency of the device. The device switched between colorless and dark violet–blue hues under applied potentials of ±1.5V. A large transmission modulation (52%, λ=605nm), a high electrochromic coloring efficiency of 533cm2C−1 at 605nm and switching times of ∼2s and good stability during 2000 cycles were reported herein. The electrochemical activity of the ECD improved when it was maintained at an elevated temperature of 70°C, with no sign of thermal degradation. Furthermore, we also present the ability of this new viologen to function as an excellent redox mediator as we achieved an 86% enhancement in the power conversion efficiency of a solution processed solar cell, by its’ addition in the electrolyte. Our studies demonstrate this new viologen to be a highly versatile electroactive material which can be useful for both electrochromics and photovoltaics.

Low-cost and scalable embedded nonvolatile memory using quasi-planar bulk transistor with standard CMOS gate stacks

We propose a low-cost and highly scalable embedded nonvolatile memory using a quasi-planar bulk transistor fabricated with a standard CMOS process. Program and erase operation was achieved by hot-electron injection into the gate dielectric and drain-assisted hot-hole injection and/or electron ejection, respectively. Thanks to the electric field concentration at the channel corners in quasi-planar bulk transistor, not only the program efficiency, but also the erase efficiency was enhanced with the decrease in channel width. Scaling of gate length also improved the program and erase characteristics. As a result, a threshold voltage window of more than 0.3 V was repeatedly attained. Moreover, 300 program and erase cycles and 10-year data retention were experimentally demonstrated. Thus, quasi-planar bulk Tr. memory was found to be highly suitable for nonvolatile memory embedded with low-power scaled CMOS.

Physical modeling of program and erase speeds of metal–oxide–nitride–oxide–silicon cells with three-dimensional gate-all-around architecture

We present an investigation of the program and erase speed characteristics of three-dimensional (3D) gate-all-around (GAA) metal–oxide–SiNX–oxide–silicon (MONOS) cells. The effect of the tunneling oxide layer thickness in 3D GAA MONOS cells has been experimentally investigated and studied by 3D technology computer-aided design (TCAD) simulation. In particular, we considered physical parameters such as trap density, capture cross section, and trap level in order to analyze the physical properties of the silicon nitride layer. Simulation results indicated that the trap density significantly affects the program efficiency compared with other physical parameters, and the trap level mainly affects the erase efficiency. From these simulation results, we confirmed from the experimental results that the modeling accuracy is about 80%. Moreover, the simulation results for the program and erase speeds of the GAA MONOS cells were in reasonable agreement with experimental results.

Electrochromism of the Langmuir–Blodgett films based on monophthalocyanines carrying redox active metal centers

In this study, electrochromic properties of metallophthalocyanine (MPc)-based thin films were investigated in detail with electrochemical, in situ spectroelectrochemical and in situ electrocolorimetric analysis methods. Electrochemical and spectroelectrochemical measurements of monophthalocyanines exhibited that incorporation of redox active metal centers, CoII, FeIIIOAc, and MnIIIOAc, into the phthalocyanine center increases the redox richness of the complex due to the reversible metal-based reduction and oxidation couples of the metal centers. Metal based redox processes of the complexes affect the optical changes more than the Pc based redox process due to the shifting of the existence bands and appearance of new bands in the UV–vis spectrum. Optical changes especially in the visible part of the light spectrum are desired properties for usage of a material in the display technologies. Electrochromic measurements indicate that film formation methods, electrolytes, and nature of the metal ions in the phthalocyanine cavity alter the basic electrochromic parameters of the complexes. Langmuir–Blodgett films of manganese, cobalt, and iron phthalocyanines are found as ideal neutral and anodic coloring electrochromic materials due to their short color change times, long-term stability, and long-term write–erase efficiency.

Impact of Charge Trapping Layer Thickness and New Trade-Off in Performance Characteristics of 3-D SONOS Devices

We evaluate the impact of silicon nitride (SiN) layer thickness in BiCS-like 3-D SONOS devices via standard and advanced characterization techniques, based on program (erase) efficiency measurements. SiN thickness below 4 nm strongly impacts electron trapping efficiency, resulting in degraded program operation but enhanced erase saturation level and hence giving rise to a new program-erase trade-off. An optimal 4 nm SiN thickness is assessed for proper MLC operation.

BE-TANOS: Feasibility and technology limitations

The aim of this work is to investigate the physical mechanisms behind the write/erase and retention performances of band gap engineering (BE) layers used as tunnel oxide in charge trap memory stack. The investigation of the BE layers alone will be completed with the analyses of its integration within a TANOS (TaN/Alumina/Nitride/Oxide/Silicon) stack, pointing out the correlation between electrical performance and reliability limits. Good write/erase/retention performances can be achieved with BE tunnel oxide by using silicon nitride layer integrated in SiO 2–Si 3N 4–SiO 2 stack, as long as all different mechanisms are taken into account in optimizing stack composition: hole injection which improves erase efficiency, charge trapping and de-trapping from the thin silicon nitride which causes program instabilities and initial charge loss which does not significantly impact long term retention. All these phenomena make very crucial the BE tunnel process control and difficult its use for multi-level application.

Effect of Floating-Gate Polysilicon Depletion on the Erase Efficiency of nand Flash Memories

This letter presents a detailed experimental investigation of the erase transients of decananometer NAND Flash memories, showing a drop and then a recovery of the erase efficiency as the erase bias is increased. The modulation of the erase efficiency is studied as a function of the erase time, temperature, and the number of applied pulses: Longer erase times or higher temperatures are shown to reduce the efficiency drop, while this is enhanced when the erase pulse is split into a sequence of short pulses. Experimental evidences are explained as a result of the deep-depletion condition that exists in the floating-gate polysilicon for moderate erase biases and short erase times, reducing the electric field in the tunnel oxide and the electron-tunneling current discharging the floating gate.

A Novel Field-Enhanced-Nanowire Poly-Si Thin-Film Transistor Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory with Gate-All-Around Structure Has Been Proposed to Achieve a Higher Program and Erase Efficiency

not Available.

The Effect of Fixed Oxide Charge in Al[sub 2]O[sub 3] Blocking Dielectric on Memory Properties of Charge Trap Flash Memory Devices

In this article, we report the effect of fixed oxide charge in Al 2 O 3 blocking dielectric on memory properties of charge trap flash memory devices using Fowler-Nordheim program/erase mode. It was found that negative fixed oxide charges in the Al 2 O 3 dielectric play a crucial role in improving erase efficiency of Al 2 O 3 /SiN/SiO 2 (ANO) stacks, and thus reinforces the advantages of a Al 2 O 3 blocking layer for charge trap flash devices. Compared to n + poly-Si/ONO stack, process-optimized ANO stack with high work-function metal gate shows dramatic improvements in retention vs minimum erase state.

High Work-Function Metal Gate and High-<tex>$kappa$</tex>Dielectrics for Charge Trap Flash Memory Device Applications

We report the impact of high work-function (/spl Phi//sub M/) metal gate and high-/spl kappa/ dielectrics on memory properties of NAND-type charge trap Flash (CTF) memory devices. In this paper, theoretical and experimental studies show that high /spl Phi//sub M/ gate and high permittivity (high-/spl kappa/) dielectrics play a key role in eliminating electron back tunneling though the blocking dielectric during the erase operation. Techniques to improve erase efficiency of CTF memory devices with a fixed metal gate by employing various chemicals and structures are introduced and those mechanisms are discussed. Though process optimization of high /spl Phi//sub M/ gate and high-/spl kappa/ materials, enhanced CTF device characteristics such as high speed, large memory window, and good reliability characteristics of the CTF devices are obtained.