Erase Cycling Research Articles

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory.

To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced by erasing disturbance of the dummy WLs at the joint region (Joint-DMYs) under multiple cycling. More specifically, after several erase cycling stresses, the increasing joint-DMY's threshold voltage (Vt) due to the operational stress will finally result in additional disturbance to the adjacent data WLs. In this paper, we proposed this disturbance during erase originates from the backward injected electrons through FN tunneling based on our TCAD simulation result. Moreover, we also proposed an optimal erase scheme to reduce the backward electron injection and suppress the abnormal joint-DMY disturbance during the erase cycling.

EXPRESS: Exploiting Energy–Accuracy Tradeoffs in 3D NAND Flash Memory for Energy-Efficient Storage

The density and cost-effectiveness of flash memory chips continue to increase, driven by: (a) The continuous physical scaling of memory cells in a single layer; (b) The vertical stacking of multiple layers; and (c) Logical scaling through storing multiple bits of information in a single memory cell. The physical properties of flash memories impose disproportionate latency and energy expenditures to ensure the high integrity of the data during flash memory writes. This paper experimentally explores this disproportionality on state-of-the-art commercial 3D NAND flash memories and introduces EXPRESS—a technique for increasing the energy efficiency of flash memory writes by exploiting the premature termination of the flash write operations. An experimental evaluation shows that EXPRESS reduces energy expenditures by 20–50%, relative to the traditional flash writes, at the cost of a minimal loss in the data integrity (<1%). In addition, we evaluate the effects of the page-to-page variability, program–erase cycling, and data retention on the implementation of EXPRESS, and we propose enhancements to counter these effects.

Investigation of Program Noise in Charge Trap Based 3D NAND Flash Memory

The mechanisms and characteristics of program noise (PN) in charge trap based 3D NAND flash memory are investigated in this work. Electron injection statistics is found to be primarily responsible for PN. Moreover, it is found that PN gets worse after program and erase (PE) cycling in 3D charge trapping memory devices. A physical model is proposed to explain the observations. After heavy cycling stress, new traps are generated in the tunnel oxide, and more charges can be trapped. As a result, program speed increases and charge centroid shifts towards the tunnel oxide, which lead to worse PN. Furthermore, the upper part of Vt distribution is broadened after heavy PE cycling. The contribution of the worse PN to the upper part broadening after cycling is studied through Monte Carlo simulation.

Investigation of Erase Cycling Induced TSG Vt Shift in 3D NAND Flash Memory

Erase cycling induced Vt shift of top select gate transistor (TSG) and its physical mechanism are studied in 3D NAND flash memory. It is found that the distribution of TSG Vt shifts higher during memory cells erase cycling. Furthermore, the TSG Vt shift can recover after the removal of cycling stress. A physical model of trap generation induced by hot holes is proposed for above observations. It is considered that hot holes generated by high channel potential gradient during erase can break the $\equiv $ Si–H bonds at the poly-Si grain boundary and the poly-Si/SiO2 interface, causing TSG Vt tail shift and parallel shift, respectively. And the degradation can recover due to re-passivation of $\equiv $ Si–H bonds after stress removal. A TSG bias optimization scheme is demonstrated to reduce the hot holes generation and suppress the TSG abnormal Vt shift during cell erase cycling.

Evaluation of the Role of Deep Trap State Using Analytical Model in the Program/Erase Cycling of NAND Flash Memory and Its Process Dependence

A method to analyze the kinetics of the charge accumulation in the tunnel oxide by the nand flash memory program and erase (P/E) cycling is proposed. Both electron trapping and detrapping processes are required to be considered owing to the oxide high electric field during P/E cycles. Consequently, the electron trapping in the deep trap state is concluded, whose trap energy ( $\text{E}_{\text {trap}}$ ) is more than 3.5 eV. Furthermore, the as-grown trap state density ( ${\text{N}}_{e}$ ), the trapping capture cross section ( $\sigma $ ), and the number of trapped positive charges can also be extracted to explain the tunneling current modulation and the $\text{V}_{\text {T}}$ shift by oxide-trapped charges under the P/E stress. The trapped electrons are mainly distributed in the center of tunnel oxide, and the distributed area extends as the P/E bias increases. In addition, the dependence of oxidation process is also shown. Both thermal dry and plasma oxidation have almost the same value of $\sigma $ ( $\sim {4} \times {10}^{ {-17}}$ cm2). However, 30% reduction of ${\text{N}}_{e}$ is shown in plasma oxidation ( $\sim {1.25} \times {10}^{ {19}}$ cm−3) when compared with thermal dry oxidation ( $\sim {1.88} \times {10}^{ {19}}$ cm−3).

Low voltage cycling of programmable metallization cell memory devices

Future nanoscale memory technologies must ultimately be able to operate atpower supply voltages in the order of 0.6 V or less. We have demonstratedin this work that it is possible to utilize symmetric program–erase (P–E)cycling for Ag/Ag–Ge–S/W programmable metallization cell devices at voltagesbelow 0.6 V and still maintain an OFF/ON resistance ratio well in excessor 10 over a wide range of program and erase currents (0.27, 1.6, 55 and 220 µA) as set by a series resistance. The distributions of resistance values for104 P–E cycles indicate that the margins between the highest on- and lowest off-state resistancesare sufficient for unambiguous differentiation in all but the lowest current case in which there issome overlap. In addition, there is no substantial change in switching speed for up to1.5 × 106 P–E operations, the maximum number of cycles attempted in this study.

A study of cycling induced degradation mechanisms in Si nanocrystal memory devices

The endurance of Si nanocrystal memory devices under Fowler–Nordheimprogram and erase (P/E) cycling is investigated. Both threshold voltage (Vth) and subthreshold swing (SS) degradation are observed when using a high programor erase voltage. The change of SS is found to be proportional to the shift ofVth, indicating that the generation of interface traps plays a dominant role. The chargepumping and the mid-gap voltage methods have been used to analyze endurancedegradation both qualitatively and quantitatively. It is concluded that high erase voltagecauses severe threshold voltage degradation by generating more interface traps and trappedoxide charges.

Investigation of the Channel-Width Dependence of CHEI Program/HHI Erase Cycling Behavior in Nitride-Based Charge-Trapping Flash (CTF) Memory Devices

Investigation of the Channel-Width Dependence of CHEI Program/HHI Erase Cycling Behavior in Nitride-Based Charge-Trapping Flash (CTF) Memory Devices

Write/Erase Cycling Endurance of Memory Cells With SiO<tex>$_2$</tex>/HfO<tex>$_2$</tex>Tunnel Dielectric

The write/erase cycling endurance of low voltage floating-gate memory cells programmed and erased by tunneling through a SiO/sub 2//HfO/sub 2/ dual layer tunnel dielectric stack is investigated. The use of fixed single pulse program and erase conditions leads to fast shifting (after /spl sim/1000 cycles) of the threshold voltage window, so that only a limited number of write/erase cycles can be achieved. Increasing the write and erase duration quickly leads to an excessive erase time so that a different erase method has to be used. Improvement of the erase behavior and cycling endurance has been obtained by a combination of two methods. Inclusion of soft write pulses between the erase pulses reduces the amount of charge trapped in the tunnel dielectric and therefore limits the increase in erase time. Also, the erase voltage can progressively be raised in order to further limit the erase time, leading to an endurance of 10 000 cycles on the considered cells. When combining the SiO/sub 2//HfO/sub 2/ stack with channel hot electron injection so that tunneling is only required in one direction, 100 000 write/erase cycles are demonstrated with minimal change of the memory window.

Characterization of moving bits (MBs) and QBD in wet/dry tunnel oxides for floating gate type nonvolatile memory (FG-NVM) applications

A critical problem of floating gate type nonvolatile memories (FG-NVMs) used in flash memories or EEPROMs is anomalous charge loss which leads to threshold voltage ( V t) shifts on a time scale of months or years at room temperature. The number of these moving bits (MB's) is greatly affected by the nature and properties of the tunnel oxide that is used in the NVM technology. In this paper we compare different types of tunnel oxides and determine the impact on the MB issue with different measurement techniques. The appearance of MB is demonstrated by a low electric field test. This test is a close match to real lifetime conditions and as such gives a good indication of the MB performance of the device. Nevertheless since this test is very time consuming it is not feasible to use it for monitoring during manufacturing. It is demonstrated that a fast QBD measurement correlates very well with MB test itself. As such the QBD test is a valid tool for fast NVM reliability evaluation. Oxide leakage measurements, on the other hand, do not give any indication of MB characteristics. Wet oxide grown at 750 °C proves to be far superior in terms of MB performance compared to the dry oxides grown at 900 or 960 °C. The initial MB measurements before write–erase cycling show a strong impact of the thickness and the type of oxide. This is still valid after 10K write–erase cycles: increasing the thickness of the tunnel oxide from 7.5 to 10 nm decreases the number of MB's by at least three orders of magnitude. After 10K cycles, one order of magnitude less MB's are observed for the wet oxide versus the dry oxide.