Abstract
Erase cycling induced Vt shift of top select gate transistor (TSG) and its physical mechanism are studied in 3D NAND flash memory. It is found that the distribution of TSG Vt shifts higher during memory cells erase cycling. Furthermore, the TSG Vt shift can recover after the removal of cycling stress. A physical model of trap generation induced by hot holes is proposed for above observations. It is considered that hot holes generated by high channel potential gradient during erase can break the $\equiv $ Si–H bonds at the poly-Si grain boundary and the poly-Si/SiO2 interface, causing TSG Vt tail shift and parallel shift, respectively. And the degradation can recover due to re-passivation of $\equiv $ Si–H bonds after stress removal. A TSG bias optimization scheme is demonstrated to reduce the hot holes generation and suppress the TSG abnormal Vt shift during cell erase cycling.
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