Capacitor Equivalent Series Resistance Research Articles

Online condition monitoring for DC-link capacitors of three-level NPC converters using noninvasive signal injection

This paper introduces an online method for monitoring the health condition of the DC-link in three-level NPC converters. This method does not require hardware changes or modifications to the control algorithm. It involves injecting a zero-sequence signal, added to the system reference voltages to generate a neutral-point current injection. A square waveform with an interharmonic cycle frequency is used for the signal injection to minimize estimation errors caused by existing signals. This combined signal allows for the simultaneous estimation of the capacitor equivalent series resistance (ESR) and capacitance (C) at different frequency components using wavelet decomposition. Additionally, a balance between the magnitudes of the system reference voltage and the signal injection is established to prevent power quality issues. Besides, the capacitor parameters are estimated in the time-frequency domain, enabling tracking of capacitor degradation and wear-out failure. A comparison with a Fourier-based approach shows that this method provides highly accurate capacitor parameter estimation with less than 2% errors, instilling confidence in its results. Experimental results from a three-level NPC converter’s laboratory setup demonstrate the proposed method’s effectiveness.

Challenges in Measurement of Low-Value ESL and ESR of High-Performance PFN Capacitors for Klystron Modulator

In the high voltage line type pulse modulators, Pulse Forming Network (PFN) capacitors are one of the important components. These capacitors operate at peak kilo ampere current range and at repetition rate in the range of a few hundred hertz. The performance of these capacitors is critical w.r.t. overall system performance, and they are required to operate at high power density and low losses with high reliability. The Equivalent Series Inductance (ESL) and Equivalent Series Resistance (ESR) are two critical parameters that affect the performance of these capacitors. PFN modulator demands a capacitor of very low ESL and ESR for reliable operation and generation of high-voltage pulses. Higher ESR value adversely affects the performance of the capacitor by raising its temperature and thus deteriorating its life. ESL value does not directly affect life, but it affects the quality of high voltage pulse. In RRCAT, the PFN capacitors purchased from Indian manufacturers were showing high-temperature rise and failures. Therefore, new capacitors were designed to have lower ESL and ESR values. Measurement of ESL and ESR is important to evaluate the performance of the capacitors. The low value of these parameters makes their measurement a challenging task and requires special techniques. For low values of ESL and ESR (less than 100 mΩ) measurement, a differential measurement technique was used in which modification and different layouts were explored to improve the repetitive accuracy of the measurements. The differential ESR and ESL measurement techniques with more emphasis on the low-value ESR measurement will be discussed in the paper.

Online Cell Capacitance and ESR Monitoring Using Switching Frequency in a Modular Multilevel Converter

A cell capacitor is one of the most fragile components in a modular multilevel converter (MMC). Capacitance decreases and equivalent series resistance (ESR) increases, as the capacitor deteriorates. This paper proposes an online monitoring method for both the capacitance and ESR of the cell capacitors in an MMC without any additional components or operation. The proposed method measures the impedance of the cell capacitor not only at a low frequency but also at a switching sideband-frequency of the cell without current sensors for capacitor current. The high-frequency components around the switching frequency improve the estimation accuracy compared with the previous methods that measure only impedance at low frequencies. The experimental results confirm that the proposed method estimates the capacitance and ESR with errors of 3.1% and 8.8%, respectively.

Improved dynamic performance with discrete sampling in digital ACM controlled DC‐DC boost converter with capacitor ESR inclusion

AbstractA classical symmetrical carrier‐based digital Average Current Mode (ACM) control has two sampling choices, peak point and valley point, to control the average inductor current. If it is employed to regulate the DC‐DC boost converter, there will be a difference in the dynamic performance at peak and valley point sampling instants because of discontinuous output voltage ripple due to Equivalent Series Resistance (ESR) of the output capacitor. Therefore, this paper investigates the effect of sampling instant on the dynamic performance of the PWM DC‐DC boost converter in consideration of capacitor ESR. The small‐signal transfer functions of a boost converter for both sampling positions are prominent to analyze each sampling impact on its dynamics. They are derived by using discrete‐time modeling. Further, the choices of sampling instant are investigated related to the RHP zero elimination, voltage stability, and peak‐to‐peak ripple current of the DC‐DC boost converter. The boost converter has improved stability performance by synchronizing the ADC sampling at starting position (valley point) of the symmetrical carrier signal, as evident by the analytical and hardware results of both sampling techniques working from 25% to 100% load working conditions.

Firmware-based Capacitor and Equivalent Series Resistance (ESR) Meter

This paper presents the development of a capacitor ESR meter, which covers capacitance and ESR measurements as well as the interrelationship of the constituent parts/circuits. The idea is to keep the hardware design simple, transferring the complexity to firmware which controls the hardware. In particular, it uses automatic functions controlled by relays thus there is no need for switches and its automatic calibration ensures there is no need for menus. This work covers voltmeter function, C/R time constant function and ESR function using Arduino Uno boards. Each firmware code was developed one after the other, starting with the voltmeter function then C/R time constant function and finally ESR function. Results were checked by serial data transfer from Arduino Uno board to the laptop that is running the Arduino compiler with terminal. One Arduino Nano interface was constructed to interface the project shield. The firmware was developed to provide the voltmeter function, C/R time constant function and ESR function. An organic light-emitting diode (OLED) display was used to show measurement results. Logic control was added to provide the required functions to work as intended, as well as an automatic short circuit detection at DUT terminals firmware which includes a calibration cycle. Conventional ESR meters are usually have complex hardware, in contrast the design presented in this work shifts the focus to the firmware so that hardware is uncomplicated. This reduces the cost that typically comes with more hardware components. Keywords : Capacitor, ESR Meter, C-R Time Constant, Arduino, OLED Display, Calibration DOI: 10.7176/CEIS/13-1-02 Publication date: January 31 st 2022

Online ESR Monitoring of DC-Link Capacitor in Voltage-Source-Converter Using Damping Characteristic of Switching Ringings

Online monitoring of dc-link capacitor's equivalent series resistance (ESR) could provide valuable and timely information for power converter failure prognosis and predictive maintenance. The conventional ESR estimation methods are mainly based on pulsewidth modulation (PWM) voltage and current ripples (ESR≈Δu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> /Δi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ), but the performance is affected by operating conditions (especially at light-load), quasi-resonance effect and sensor amplitude error. To overcome these difficulties, an online ESR monitoring method is proposed using the damping characteristic of dc capacitor switching ringings. The intrinsic high-frequency (HF) resonance incidents between the power device fast switching and converter parasitic parameters are utilized in this article. First, the mechanism of dc capacitor switching ringing is analyzed by the HF resonance equivalent circuit. The analytic relationship between the damping characteristic and the ESR is established. Then, the condition monitoring (CM) scheme, noncontact HF sensor, and half-power bandwidth algorithm for ESR estimation are presented. Finally, an experimental study is carried out to validate the feasibility and effectiveness. The damping of switching ringing is inherently sensitive to the ESR of dc capacitor under the condition of resonance. Both theoretical analysis and experimental results confirm that the proposed method can achieve mΩ-level accuracy and good robustness under different conditions.

An Online Monitoring Scheme of Output Capacitor's Equivalent Series Resistance for Buck Converters Without Current Sensors

Aluminum electrolytic capacitors are widely used in switching mode power supply as smoothing capacitor, but they are the weakest among power components in dc–dc converter. It is very important to monitor its electrical parameters, mainly the equivalent series resistance (ESR). A monitoring method of capacitor's ESR for buck converters is proposed in this article. Based on the calculation model of ESR, the target parameter is monitored by sampling output ripple voltage. The proposed method needs no current sensor. Whether the circuit is in continuous conduction mode or discontinuous conduction mode, it is convenient to monitor the capacitor. Implementation of the monitoring system is presented. The experimental results validate the effectiveness of the method.

Stability Effect of Control Weight on Multiloop COT-Controlled Buck Converter With PI Compensator and Small Output Capacitor ESR

Multiloop constant on-time (COT) controlled buck converter uses two weight resistors for sensing inductor current and detecting output voltage in its inner loop. When an output capacitor with a small equivalent series resistance (ESR) is employed, the converter will suffer the risk of instability due to different weight settings of inductor current and output voltage using a proportional-integral (PI) compensation gain in the outer voltage loop. However, no attention has been paid for their stability effects, which are important for designing the inner loop and outer voltage loop. To address these issues, a piecewise linear model is established for multiloop COT-controlled buck converter. Circuit parameter-related bifurcation behaviors and control weight-related dynamical distributions are explored to demonstrate these stability effects. Furthermore, by deriving an approximate discrete model, a control weight-related stability criterion is expressed explicitly, from which stability boundaries for dividing the normally stable and abnormally unstable operation parameter regions are thereby yielded. Besides, control weight-related transient performances under different circuit parameter settings are analyzed. Finally, PSIM circuit simulations and hardware circuit experiments verify the theoretical analysis well.

Stability analysis of the main converter supplying a constant power load in a multi-converter system considering various parasitic elements

Multi-converter power electronic system is nowadays popular in mobile vehicular applications. Different converters behave as Constant Power Loads (CPL) in a multi-converter system. These offer a negative impedance characteristic which results in a destabilizing effect on a converter driving them. Researchers have analyzed that the Buck converter supplying a CPL is unstable, but stability can be achieved by considering Constant Voltage Load (CVL) and parasitics of converter components in the system. In this paper, the effect of CVL in parallel with CPL and parasitic of switch, diode and inductor of main converter is mathematically evaluated on system stability. Then capacitor internal resistance is considered for the further analysis and the generalized expression is derived with consideration of parasitics of switch, diode, inductor, capacitor and CVL connected in the system and consistency of the generalized expression is verified with the established cases in the literature. The effect of the equivalent series resistance of capacitor on stability is analysed and compared with the stability due to parasitic elements of switch, diode and inductor. Further minimum and maximum range of parasitic of capacitor is derived to obtain the desired stability limit for given operating condition.

Capacitor ESR and C Monitoring in Modular Multilevel Converters

The capacitor is one of the weakest components in the modular multilevel converter (MMC). The rise of equivalent series resistance (ESR) is a prominent character to monitor the lapsed capacitor, but current research works only focus on capacitance and neglect ESR of capacitors in the MMC. This article proposed a sorting-based monitoring strategy for capacitors in the MMC, which monitors not only the capacitance but also the ESR of capacitor. This article reveals the relationship among the capacitor's ESR, capacitance, current, and energy. Based on the relationship, the ESRs and capacitances of submodule capacitors in the arm are indirectly sorted, respectively, and only the capacitor with biggest ESR and the capacitor with smallest capacitance in the arm are monitored. The proposed strategy not only realizes both ESR and capacitance monitoring in the MMC, but also proposes a simplified monitoring algorithm for MMCs with a large number of capacitors. The simulation and experimental results confirm the effectiveness of the proposed monitoring strategy for MMCs.

Accelerated Degradation Test Investigation for Life-Time Performance Analysis of LED Luminaires

LED luminaires are a common lighting source used in general lighting application as they are energy-efficient and long-lasting. However, the reliability of an LED luminaire is not well established, and no standard method for estimating the performance of an LED luminaire is developed. This article presents an investigation to understand the performance of LED luminaires at the accelerated degradation test (ADT) condition and analyzes the reliability of LED luminaires. An LED luminaire has two subsystems, an LED light engine and the LED constant current driver that are subjected to ADT, and the light engine factors, lumen output, and Duv changes are analyzed. Similarly, the driver output stage electrolytic capacitor capacitance and equivalent series resistance (ESR) are estimated. The study of continuous operation in time and study when subjected to switching cycles to quantify reliability in terms of operating cycles is performed. All four key parameters-lumen maintenance, Duv, capacitance, and ESR-are estimated up to their specified threshold and reliability is analyzed. The LED light engine lumen output is found to degrade very quickly compared with other factors. LED luminaire failure at ADT is mainly due to lumen depreciation followed by color shift and, after significant intervals of time and cycles, the driver capacitor ESR follows as reason for the failure of the LED luminaire. A scanning electron microscope (SEM) energy dispersive spectroscopy (EDS) analysis is performed on the LED package, and results show that LED silver (Ag) mirror tarnish is the main reason for a significant reduction in light output.

Analysis of the DC-Link Current for the Single-Phase H-Bridge Inverter Under Harmonic Output Currents

This paper investigates the dc-link current to facilitate the dc-link capacitor sizing for the single-phase H-bridge inverter under harmonic ac currents. As the capacitor equivalent series resistance varies significantly until the frequency is higher than 1 kHz, the expressions of the dc-link current individual low-order harmonics (LOHs) and the switching harmonic currents (SHCs) root-mean-square (rms) value are derived, respectively, to accurately evaluate the dc capacitor losses. The dc-link LOH expressions reveal that each harmonic ac current induces two harmonic currents in the dc-link. When the ac current has multiple combinations of LOHs, the dc-link current envelopes take infinite possible unusual forms, so after somewhat complicated derivation, the SHCs rms equations are successfully derived and further simplified into one equation for easy worst case design as demonstrated by the actual case study. A single-phase H-bridge inverter lab prototype is developed to inject arbitrary combinations of harmonic currents of different orders, amplitudes, and angles into the grid. The good match between the computational, simulation, and experimental results validate the effectiveness of the proposed method. In particular, the worst case analysis is verified by the experiment and the differences between the experimental and computational results are formulated and explained definitely.

A Constant On-Time Control With Internal Active Ripple Compensation Strategy for Buck Converter With Ceramic Capacitors

Constant on-time control has been widely used due to its advantages of fast transient response and light load efficiency. However, the control scheme is intrinsically unstable if the output capacitor's equivalent series resistance (ESR) is not large enough, which needs ripple injection techniques to enhance loop stability. The traditional passive ripple compensation technique uses only passive component networks to realize this function, which exhibits some inherent shortcomings, including difficulties in high-speed current sensing amplifier design and large chip area consumption. This paper proposes an internal active ripple compensation strategy that senses the low-side power mosfet current and extracts relevant ac information for feedback-ripple enhancement. Output-voltage dc offset does not occur and subharmonic instability is significantly improved even with ceramic capacitors. The circuit architecture has been realized in a synchronous buck regulator with a 0.5 μm 40 V bipolar-CMOS-DMOS (BCD) process. The programmable switching frequency is up to 1 MHz and the maximum load current is 4 A. Simulation and experimental results are given to prove the proposed high performance.

A Comprehensive Monitoring System for Online Fault Diagnosis and Aging Detection of Non-Isolated DC–DC Converters’ Components

Online monitoring is an inevitable necessity for dc–dc converters in industrial applications to achieve a fault-tolerant structure, which ensures reliable operation and prevents catastrophic failures. In this paper, a comprehensive monitoring system is proposed for non-isolated dc–dc converters. The proposed approach is mainly focused on monitoring the most prone to failure components of these converters including switching devices and capacitor. Using the proposed monitoring system, switch/diode open circuit and short circuit faults are detected in less than one switching cycle. Furthermore, online monitoring of the capacitor equivalent series resistance and switch on-state voltage as effective precursors of aging is also carried out. Finally, an inter-turn fault detection technique is presented for the converter inductor. The mentioned monitoring tasks are accomplished using only two electrical sensors (for capturing voltages across the converter diode and inductor) and two temperature sensors. The presented monitoring approach is simple, cost-effective, easy to implement, and applicable for all non-isolated dc–dc converters including buck, boost, and buck-boost converters. Performance of the monitoring system is evaluated by considering different scenarios in the experiments carried out on a laboratory prototype. The results confirm the effectiveness of the proposed system for fault diagnosis and aging monitoring in non-isolated dc–dc converters.

Sensorless predictive current control with a charge balance current estimator for boost converters based on discrete‐time model considering current ripple

The performance of a sensorless predictive current controlled boost converter is usually susceptible to the accuracy of the employed converter and current estimator models. Since the accuracy of conventional current estimator would be degraded due to parasitic parameter variations, a charge balance current estimator (CBCE) is proposed to overcome this issue. Its estimation of peak inductor current is based on the charge balance principle of output capacitor and characteristics of inductor current ripple. Only one parasitic parameter - capacitor equivalent series resistance (ESR) is used in CBCE. Furthermore, the capacitor ESR is also estimated together with output load by a proposed equivalent load estimation scheme which can improve the current estimation accuracy. Besides, to achieve a high dynamic performance digital control, a discrete-time model considering current ripple is developed, in which the ripple is taken into account rather than treats inductor current as a constant in each switching cycle. It can achieve a higher accuracy than conventional averaged model, especially in the high-frequency region. Finally, its effectiveness is verified by simulation and experiment results.

Low‐power non‐ideal pulse‐width modulated DC–DC buck–boost converter: design, analysis and experimentation

In this study, parasitic elements (non-idealities) effect on a low-power DC-DC buck-boost converter design is analysed and investigation is carried out by both large (i.e. steady-state) and small signal analysis. The large signal analysis of non-ideal buck-boost converter explored the significant information such as nearly accurate duty cycle, maximum allowable duty cycle and maximum possible output voltage. Further, accurate mathematical design formulae are derived of inductor and capacitor for specified inductor current ripple and output voltage ripple (OVR), respectively. Moreover, consequences of different equivalent series resistance of capacitor on OVR is examined. Subsequently, the exact model of buck-boost converter is procured from the small signal analysis, which is almost analogous to practical system. In order to show the impact of non-idealities on controller design, an internal model control PID controller is designed for ideal, semi-non-ideal and complete non-ideal systems based on their respective models, which shows the controller based on non-ideal model provides very close results to practical system. Conclusively, the complete theoretical explorations are justified by simulations and substantiated by experimental results.

Online Condition Monitoring System for DC-Link Capacitor in Industrial Power Converters

This paper proposes an online condition monitoring system for aluminum electrolytic capacitors used as dc-link capacitors in industrial power converters. Electrolytic capacitors are one of the most fragile components of a power converter system because of their wear-out failures and short lifespan. Therefore, the use of condition monitoring systems for aluminum electrolytic capacitors allow preventive maintenance to be performed, thereby avoiding unexpected shutdown and downtime. The dominant wear-out mechanisms in aluminum electrolytic capacitors are characterized by the increase in equivalent series resistance. Hence, the condition monitoring system proposed in this paper is based on the online estimation of the capacitor's equivalent series resistance using the switching frequency components of the dc-link capacitor voltage and current. The equivalent series resistance estimation method is tested using the PSpice circuit simulator and is validated experimentally using a custom-made inverter. Finally, the equivalent series resistance estimation method is adapted for the condition monitoring of capacitors in industrial power converters and the proposed condition monitoring system is implemented in a commercial ac drive system to prove the applicability of the proposed method to industrial power converters.

Аccelerated Tests of the Storageability of Tantalum Capacitors Using the Thermal Method

С помощью ускоренного метода оценки сохраняемости конденсаторов на основе воздействия повышенной температуры среды без приложения электрической нагрузки проведены исследования на стадии производства. При проведении ускоренных испытаний при температуре 398 К (125 ºС) на конденсатор без приложения к нему электрического напряжения происходит старение оксидного слоя на танталовом аноде конденсатора. Приведена методика расчета длительности ускоренных испытаний, которая составила 28,18 ч. Испытаны 5 различных номиналов по 45 штук в каждой из 3 выборок танталовых оксидно-полупроводниковых чип-конденсаторов и 2 выборки танталовых объемно-пористых конденсаторов для выявления некачественной продукции. В процессе испытаний, соответствующих годовым циклам до 30 лет, проводились измерения параметров-критериев годности: емкости, тангенса угла потерь, тока утечки, эквивалентного последовательного сопротивления конденсаторов. Из приведенных зависимостей установлено, что в процессе хранения некоторые параметры претерпевают изменения к окончанию срока хранения, имитирующему срок более 25 лет. Отклонение от монотонной зависимости для всех выборок связаны с критическими моментами воздействия тепла. Отмечено, что наибольшие изменения претерпевает параметр тока утечки; другие параметры находятся в пределах нормы.

Bi-Stability Phenomenon in Constant On-Time Controlled Buck Converter With Small Output Capacitor ESR

This paper reports the finding of bi-stability phenomenon in a constant on-time (COT) controlled buck converter with a small output capacitor equivalent series resistance (ESR). In the previously published literatures, it has been reported that the COT controlled buck converter with a small output capacitor ESR operates in the reduced-frequency periodic oscillation state. However, it is newly validated by numerical simulations that for some specified initial states, such a buck converter with the same circuit parameters can operate in a chaotic oscillation state as well, reflecting the existence of bi-stable oscillation states. Based on the piecewise continuous model of COT controlled buck converter, the bi-stability phenomenon associated with two sets of initial states is revealed by numerical simulations and verified by PSIM circuit simulations. Consequently, when a small output capacitor ESR is used, the coexisting attractors' behavior of two bi-stable oscillation states appears in such a COT controlled buck converter, leading to the emergence of bi-stability phenomenon.

Systematic circuit design and analysis of a non‐ideal DC–DC pulse width modulation boost converter

This study presents systematic design and detailed circuit analysis of a non-ideal DC-DC pulse width modulation boost converter. An accurate mathematical formula is thrived to evaluate the duty cycle, which enables the converter to neutralise the voltage drop across the parasitic elements. Furthermore, the modified relationships for the design of inductor have been obtained, which satisfy the requirements of stipulated inductor current ripples in the presence of parasitics. Moreover, the mathematical relation is developed to design the output capacitor, which is more accurate than the conventionally derived expression. In addition to this, the output capacitor's equivalent series resistance effect on the output voltage ripples is also investigated. Finally, the experimental and simulation results are used to validate the theoretical analysis.