Epitaxial Growth Of Si Research Articles

High-temperature time-dependent dielectric breakdown of 4H-SiC MOS capacitors

—With the rapid applications of silicon carbide metal–oxide–semiconductor field-effect transistor (SiC MOSFET) power devices, further improving the performance of SiC MOSFET device through enhancing its gate oxide reliability is one of the crucial directions. The density of interface states in a SiC MOSFET is a significant parameter that affects the reliability of the gate oxide layer. In this paper, the SiC MOS capacitors (MOSCAPs) were prepared by the 1250 °C dry oxidation and 1350 °C NO annealing process. Then, we analyzed the mechanisms of the breakdown by two group of ramped experiment. And we still evaluated the reliability of oxide layer via the high-temperature time-dependent dielectric breakdown (TDDB) tests on the prepared MOSCAPs, meanwhile, the temperature effect on the reliability was considered. Furthermore, the E, 1/E, and E models with Weibull plotting were used to calculate the tBD lifetimes and failure analysis was carried on the failed samples finally. The results indicate that: (1) the impact of the generation and accumulation of the traps in the oxide, which is the main mechanisms of device failure; (2) The prediction of lifetime was calculated with three models at different acceleration factors; (3) at high-temperature, although the lower the density of interface states is, the Si epitaxial growth and C cluster will manifest in the oxide surface and lead to the breakdown of SiC MOSCAPs.

All-Epitaxial Self-Assembly of Silicon Color Centers Confined Within Sub-Nanometer Thin Layers Using Ultra-Low Temperature Epitaxy.

Silicon-based color-centers (SiCCs) have recently emerged as quantum-light sources that can be combined with telecom-range Si Photonics platforms. Unfortunately, using conventional SiCC fabrication schemes, deterministic control over the vertical emitter position is impossible due to the stochastic nature of the required ion-implantation(s). To overcome this bottleneck toward high-yield integration, a radically innovative creation method is demonstrated for various SiCCs with excellent optical quality, solely relying on the epitaxial growth of Si and C-doped Si at atypically-low temperatures in an ultra-clean growth environment. These telecom emitters can be confined within sub-nm thick epilayers embedded within a highly crystalline Si matrix at arbitrary vertical positions. Tuning growth conditions and doping, different well-known SiCC types can be selectively created, including W-centers, T-centers, G-centers, and, especially, a so far unidentified derivative of the latter, introduced as G'-center. The zero-phonon emission from G'-centers at ≈1300nm can be conveniently tuned by the C-concentration, leading to a systematic wavelength shift and linewidth narrowing toward low emitter densities, which makes both, the epitaxy-based fabrication and the G'-center particularly promising as integrable Si-based single-photon sources and spin-photon interfaces.

Characteristics of high-order silane based Si and SiGe epitaxial growth under 600 ℃

Low temperature Si and SiGe epitaxy have been crucial in the semiconductor industry, prompting interest in high-order silanes as Si precursors. In this study, we investigated the growth characteristics of Si and SiGe epitaxial layers using Si2H6, Si3H8, and Si4H10 precursors by ultra-high vacuum chemical vapor deposition at temperatures between 500℃ and 600 ℃. We examined the effects of each precursor on the growth behaviors through varying temperature and flow rate conditions. For these three precursors, activation energies for Si epitaxy were measured to be below surface H desorption energy, and an increase in the order led to a greater adatom density at equivalent flow rates. In SiGe epitaxy, we observed Ge composition variations with temperature at each Ge-to-Si flow ratio depending on the Si precursors. Si2H6 exhibited almost consistent Ge compositions across temperatures, and the activation energy for SiGe epitaxy was decreased to 1.73 eV when the flow ratio was increased to 1. In comparison, Si3H8 and Si4H10 exhibited negligible changes in Ge compositions for the flow ratios below 0.5, with activation energies of 1.88 and 1.62 eV, respectively. Based on our experimental results, we proposed potential reaction pathways for high-order silane precursors.

Pattern formation via the oriented growth of Au-Si thin films on Si(001) substrate

The fabrication of patterned surfaces is integral to various device manufacturing processes. These techniques, developed over time, enable the precise manipulation of surface properties at the nanoscale. In this study, we introduce a self-driven approach for patterning metal and semiconductor surfaces by solidifying eutectic Au-Si thin films on Si(001) substrates. The resulting pattern encompasses meticulously aligned rectangular Au-Si eutectic structures and Si islands, the orientations of which are determined by the substrate. This exceptional alignment is attributed to the epitaxial growth of Si(001) and the heteroepitaxial growth of Au(001) and Au(011) within the films. This conclusion was corroborated through selected area electron diffraction and synchrotron radiation grazing-incidence wide-angle X-ray scattering (GIWAXS). We propose a 4:3 coincident site lattice (CSL) model to elucidate the Au-Si interface, explaining the dominant (001)[110]Au||(001)[110]Si orientation relationship that minimizes the Au/Si lattice mismatch to 0.2%. The other observed orientation relationships, (110)[001]Au||(001)[110]Si and (001)[010]Au||(001)[110]Si, entail a 6.3% mismatch in one or two directions, leading to contrasting elastic strains in the Au and Si lattices, accompanied by the accrual of elastic strain energy. This study underscores the practicality of substrate-oriented pattern formation, with potential applications in other phase-separated systems.

Phase evolution in epitaxial Gd2O3 due to anneal temperature for silicon on insulator application

Epitaxial growth of Si on rare-earth oxides on Si wafer using sputter technology promises cheaper and high-volume manufacturing of Silicon-on-insulator (SOI) wafers over costly solutions like the smart-cut method. Further, rapid thermal annealing (RTA) in standard complementary metal–oxide–semiconductor (CMOS) processing affects the performance of SOI substrate through chemical and crystal phase change. Herein, we present a systematic study on the rich physical and chemical phase evolution of epitaxial Gd2O3 grown on Si (111) using RF sputtering subjected to RTA temperatures (850−1050 °C). First, X-ray diffraction analysis shows a significant enhancement of the epitaxial cubic phase in as-deposited Gd2O3 at an optimum RTA temperature of 850 °C, which is partially explained by epitaxial-regrowth of an amorphous layer at Gd2O3/Si interface as observed in Transmission Electron Microscopy. Secondly, the degradation of crystallinity beyond 900 °C is correlated with temperature-dependent Si diffusion into Gd2O3 that becomes observable by X-ray photoelectron spectroscopy. The Gd2O3 crystallinity is completely quenched into the amorphous gadolinium silicate phase at 1050 °C. Eventually, we employed X-ray reflectivity modeling to evaluate the film thickness variation with RTA. This study provides a detailed insight into the structural and chemical dynamics occurring in epitaxial-Gd2O3 film for CMOS-relevant temperatures.

Low-Temperature Epitaxial Growth by Quiescent Plasma-Enhanced Chemical Vapor Deposition at Atmospheric Pressure

Atmospheric pressure (AP) plasma provides an alternative approach to low-cost thin-film deposition. The low throughput of epitaxial growth, which limits productivity in semiconductor manufacturing, can be addressed by using AP plasma. In principle, AP plasma does no damage and enables local heating of the deposition surface. In Si epitaxial growth using AP plasma, hydrogen incorporation and quiescent gas flow are shown to be key factors controlling epitaxial growth even under a high environmental impurity flux and at a low substrate temperature of 150 °C. Quiescent plasma at AP is promising for future epitaxial processing owing to its low cost and high productivity.

Comprehensive Analysis of Phosphorus-Doped Silicon Annealed by Continuous-Wave Laser Beam at High Scan Speed.

We report an in-depth analysis of phosphorus (P)-doped silicon (Si) with a continuous-wave laser source using a high scan speed to increase the performance of semiconductor devices. We systematically characterized the P-doped Si annealed at different laser powers using four-point probe resistance measurement, transmission electron microscopy (TEM), secondary-ion mass spectroscopy, X-ray diffractometry (XRD), and atomic force microscopy (AFM). Notably, a significant reduction in sheet resistance was observed after laser annealing, which indicated the improved electrical properties of Si. TEM images confirmed the epitaxial growth of Si in an upward direction without a polycrystalline structure. Furthermore, we observed the activation of P without diffusion, irrespective of the laser power in the secondary-ion mass-spectrometry characterization. We detected negligible changes in lattice spacing for the main (400) XRD peak, showing an insignificant effect of the laser annealing on the strain. AFM images of the annealed samples in comparison with those of the as-implanted sample showed that the laser annealing did not significantly change the surface roughness. This study provides an excellent heating method with high potential to achieve an extremely low sheet resistance without diffusion of the dopant under a very high scan speed for industrial applications.

Study of phosphorus-doped Si annealed by a multi-wavelength laser

Activation annealing of phosphorus (P)-doped Si was performed with a red–greenblue (RGB) laser to evaluate its potential for the uniform heating of patterned semiconductor devices. Various characteristics of P-doped Si annealed by an RGB laser were experimentally investigated. In addition, a numerical simulation of the multi-wavelength laser annealing process was conducted to predict the temperature distribution during the process. The electrical and crystalline properties were significantly affected by the laser power. Additionally, the wavelength combination considerably affected the electrical and crystalline characteristics under moderate laser powers (27–28 W). However, the effects of the laser power and wavelength on the atomic structure were negligible. Substantial P redistribution and an increase in the surface roughness were only observed for the highest laser power (30 W) using the RGB wavelength, resulting in the highest temperature (∼2076 K) in the simulation. Under this condition, complete melting beyond end-of-range defect zone occurred, leading to a full epitaxial growth of Si and a very low sheet resistance. According to the simulation results, for the same laser power, the RGB wavelength exhibited a higher temperature than the RB wavelength because of the high absorption rate of the green laser in Si.

Application of an Electrical Low Pressure Impactor (ELPI) for Residual Particle Measurement in an Epitaxial Growth Reactor

The purpose of this study was to determine the feasibility of using an electrical low pressure impactor (ELPI) for analyzing residual particles in a Si epitaxial growth process chamber and establish an application technique. Prior to experimental measurements, some preliminary works were conducted, including an inlet improvement of a cascade impactor, vacuum fitting fastening and flow rate adjustment, and a vacuum leak test. After that, residual particles in the process chamber were measured during N2 gas purge using an ELPI due to its advantages including the real-time measurement of particles and the ability to separate and collect particles by their diameters. In addition, ELPI could be used to obtain particle size distribution and see the distribution trend for both number and mass concentration. The results of the real-time analysis of the total particle count revealed that the concentration at the endpoint compared to that at the beginning of the measurement by decreased 36.9%. Scanning electron microscopy/energy-dispersive X-ray spectroscopy (SEM–EDS) analysis of collected particles was performed using two types of substrates: Al foil and a Si wafer. The results showed that most particles were Si particles, while few particles had Si and Cl components. ELPI has the clear advantages of real-time particle concentration measurement and simultaneous collection. Thus, we believe that it can be more actively used for particle measurement and analysis in the semiconductor industry, which has many critical micro/nanoparticle issues.

Epitaxial Growth of Si and SiGe Using High-Order Silanes without a Carrier Gas at Low Temperatures via UHVCVD and LPCVD

Conventional Si or SiGe epitaxy via chemical vapor deposition is performed at high temperatures with a large amount of hydrogen gas using silane (SiH4) or dichlorosilane (SiCl2H2) precursors. These conventional precursors show low growth rates at low temperatures, particularly below 500 °C although a low thermal budget becomes more important for modern fabrication techniques. High-order silane precursors, such as disilane, trisilane, and tetrasilane, are candidates for low-temperature epitaxy due to the lower strength of the Si-Si bonds compared to that of the Si-H bonds. In addition, the consumption of vast amounts of hydrogen gas is an additional burden of the low-temperature process due to its low throughput. In this study, we explored Si and SiGe epitaxial growth behaviors using several high-order silanes under ultra-high vacuum chemical vapor deposition (UHVCVD) and low-pressure chemical vapor deposition (LPCVD) conditions without a carrier gas. Disilane showed high-quality epi-growth under both pressure conditions, whereas trisilane and tetrasilane showed enhanced growth rates and lower quality.

Epitaxial Growth of Ordered In-Plane Si and Ge Nanowires on Si (001).

Controllable growth of wafer-scale in-plane nanowires (NWs) is a prerequisite for achieving addressable and scalable NW-based quantum devices. Here, by introducing molecular beam epitaxy on patterned Si structures, we demonstrate the wafer-scale epitaxial growth of site-controlled in-plane Si, SiGe, and Ge/Si core/shell NW arrays on Si (001) substrate. The epitaxially grown Si, SiGe, and Ge/Si core/shell NW are highly homogeneous with well-defined facets. Suspended Si NWs with four {111} facets and a side width of about 25 nm are observed. Characterizations including high resolution transmission electron microscopy (HRTEM) confirm the high quality of these epitaxial NWs.

Formation of self-assembled Gd2O3 nanowire-like structures during epitaxial growth on Si(001).

The structural and morphological properties of gadolinium oxide (Gd2O3) grown at high temperatures with molecular beam epitaxy on Si(001) were investigated for different stages of growth. The Gd2O3 layers were grown at 850 °C with different oxygen partial pressures and substrate miscuts. RHEED and XRD investigations indicate an initial formation of silicide and a subsequent transformation into cubic Gd2O3 with (110) orientation. The surface exhibits nanowire-like structures oriented orthogonally along with the [110] directions of the substrate, as indicated by AFM. Since on 4° off-cut Si(001) substrates the nanowire-like structures are mainly oriented in only one [110] direction, the orientation of the formed Gd2O3 structures seems to be related to the dimer orientation of the (2 × 1) reconstructed Si(001) surface. The density and length of the nanowire-like structures can be tuned by a change in oxygen partial pressure. The results were discussed in terms of different physical effects, where a combination of desorption of silicon and the formation of a silicide layer in the initial stage of growth could be the reason for the growth behaviour, which is also supported through TEM investigations.

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

We describe challenges of the epitaxial Si-cap/Si0.75Ge0.25//Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-growth on top of strained Si0.75Ge0.25, even for thinner Si0.75Ge0.25 layers and when growing the Si-cap layer at a lower temperature. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap/Si0.75Ge0.25//Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer-to-wafer bonding and Si-substrate and Si0.75Ge0.25 backside removal.

Strategic Review on Different Materials for FinFET Structure Performance Optimization

In this paper, the strategic review of different materials that are used in FinFET structure is studied. This is achieved by using carefully designed source/drain spacers and doped extensions to mitigate the off-current, typically high in narrow band-gap materials, as part of a CMOS compatible replacement-metal gate process flow. FinFETs are promising substitutes for bulk complementary metal oxide semiconductor. FinFETs are dual-gate devices and Good electrostatic characteristics which are obtained in a wide range of device dimensions. The simulations provide further insights into device functionality and about the dominant off-state leakage mechanisms. The GaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. In this various types of materials are used and studied they are FinFET based Dual KK-structure, InGaAs-on-Insulator FinFET, Double Gate based n-FinFET using Hafnium oxide, SOI-FinFETs, MosFET (Multi gate), Deeply Scaled CMOS, FinFET, Selective Epitaxial Si Growth in FinFET and Atomic Layer Deposition (ALD) in FinFET. Furthermore, we demonstrate a controlled GaAs digital etching process to create doped extensions below the source-drain spacer regions.

Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer

In this work we study the epitaxial Si growth with Si2H6 for Ge surface passivation in CMOS devices. The Si-caps are grown on Ge in the hydrogen desorption limited regime at a nominal temperature of 400 °C. We evaluate the process window for the interface state density and show that there is an optimal Si-cap thickness between 8 and 9 monolayers for Dit < 5·1011 cm−2 eV−1. Moreover, we discuss the strong impact of the Si-cap growth time and temperature on the interface state density, which arises from the Si thickness dependence on these growth parameters. Furthermore, we successfully transfer a TmSiO/Tm2O3/HfO2 gate stack process from Si to Ge devices with optimized Si-cap, yielding interface state density of 3·1011 eV−1 cm−2 and a significant improvement in oxide trap density compared to GeOx passivation.

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

Three-dimensional System-On-Chip (3D-SoC) technology schemes require wafer-to-wafer bonding combined with good control of the Si thickness and the Si within wafer uniformity [1,2]. As a result, there is a renewed interest in epitaxial strained Si1-xGex as etch stop layer [3]. Epitaxial growth by means of Chemical Vapor Deposition (CVD) offers excellent control of layer thickness and material composition. If needed, the Si cap layer can be in-situ doped. The challenge is to develop low cost epitaxial growth processes without compromising the material quality. Indeed, relaxation of the Si1-xGex layer must be avoided as the presence of threading dislocations in the Si-cap has a detrimental effect on electrical properties and the yield of the devices fabricated afterwards. On the other hand, the Ge concentration in the Si1-xGex layer should be sufficiently high to guarantee etch selectivity with respect to the underlying Si substrate [4]. The Si1-xGex layer also needs to be relatively thick as some material loss cannot be avoided. Etching of the Si-cap layer during wafer back-side thinning must be prevented.In this contribution, we discuss the different challenges for the epitaxial growth of such Si-cap / Si1-xGex // Si-substrate layer stacks, with Si-cap layer thicknesses ranging from 20 to 500 nm and a targeted Ge content in the Si1-xGex layer of 25%. All epi-layers discussed in this work were grown in an ASM Intrepid RP-CVD cluster tool, aiming the highest possible process throughput. To control the epitaxial material quality, fast and reliable in-line metrology and inspection techniques are required. For instance, Wostyn et al. recently reported on inline light scattering measurements, commonly used to determine wafer quality and cleanliness, and have shown that the technique is also suitable to study the crystalline quality after hetero epitaxy [5].Standard deviations in thickness below 1.5% as measured for both the Si0.74Ge0.26 and the Si-cap layers by means of Spectroscopic Ellipsometry illustrate the within wafer uniformity of the epitaxially grown layer stacks. The Si0.74Ge0.26 material quality is confirmed by the presence of well-defined Kiessig fringes on the (004) XRD spectrum. The lack of a surface crosshatch pattern in AFM and the very low haze values as obtained from light scattering measurements using the KLA Surfscan® SP3 indicate the absence of misfit dislocations in uncapped Si0.74Ge0.26 layers for thicknesses up to 100 nm. After Si capping, RSM measurements still indicate that the layer is fully strained (Fig. 1a). Moreover, no defects were detected by commercial in-line defect inspection systems such as the KLA Electron-Beam Wafer Defect Review (EDRT M) System and the automated optical inspection system. However, depending on the process conditions, enhanced haze values might be measured. This enhanced surface roughness is due to the presence of misfit dislocations as evidenced by AFM (Fig. 1b). A careful process optimization enables the deposition of Si-cap / Si0.75Ge0.25 // Si-substrate bilayers with low haze values which are completely free of misfit dislocations, still allowing a Si-cap thickness of up to 500 nm and a relative high processing throughput (Fig. 1d). Still, it is striking that in case of 300 mm substrates, layer relaxation, if present, starts at the edge of the wafer (Fig. 1c) [6]. Therefore, special care needs to be taken to ensure that no relaxation is initiated at wafer edges. Extremely sensitive characterization methods are mandatory to detect the onset of relaxation and to ensure the fabrication of defect-free epi stacks. The developed epi process was successfully implemented in 3D device integration schemes to fabricate stacked Gate All Around devices and to demonstrate functional backside integration.

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

We describe challenges of the epitaxial Si-cap / Si0.75Ge0.25 // Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-capping, even for thinner Si0.75Ge0.25 layers. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap / Si0.75Ge0.25 // Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer to wafer bonding and Si-substrate and Si0.75Ge0.25 backside removal.

Comparison of Strain Characteristics and Contact Resistances of Heavily Phosphorus‐Doped Si Formed by Phosphorus Implantation and In Situ Phosphorus‐Doped Si Epitaxial Growth

As transistor sizes reduce, the effect of contact resistivity on power consumption increases. To reduce contact resistivity, heavily phosphorus‐doped Si grown via in situ phosphorus‐doped (ISPD) Si epitaxial growth is studied actively. Laser spike annealing to the heavily phosphorus implanted (IMP) layers is demonstrated to replace ISPD Si epitaxial growth process and phosphorus profiles and strain characteristics are evaluated. Regardless of the doping method, the phosphorus concentrations of both samples and their tensile strains are equivalent. After laser annealing, the metal‐silicidation is conducted to measure contact resistivity. The Ni‐silicide formed on IMP sample has 3D clusters inducing greater morphological degradation than ISPD samples. The contact resistivity of IMP sample measured using the circular transmission line model (CTLM) (1.2–8.3 × 10−8 Ω cm2) is similar to that of the ISPD sample (1.1–5.5 × 10−8 Ω cm2) after Ni‐silicidation of the ISPD layer. This study performs strain engineering by achieving low contact resistance at lower cost while applying strain using the IMP process rather than the epitaxial process.

Calculations of selective Si epitaxial growth

Dichlorosilane (DCS) is widely used in the semiconductor industry for selective epitaxial growth (SEG) of Si. Si SEG currently requires high temperatures, on the order of 800 °C; multiple approaches have been attempted to deposit Si at lower temperature, but no viable alternatives have been found. This failure is attributed to a poor understanding of the mechanisms and the underlying factors that determine Si growth. In this study, we investigate Si SEG using DCS and HCl on a crystalline silicon (c-Si) surface as compared to on SiO2 using density functional theory. Our calculations of Si SEG reaction mechanisms illustrate three factors that contribute to selectivity. First is that surface passivation by Cl does not limit SEG growth on c-Si while it hinders nucleation on the SiO2 surface. Second is that amorphous growth at nucleation sites on the SiO2 surface is slower than epitaxial growth on c-Si. Third is that the low entropic cost of epitaxial growth on c-Si is important for selectivity. The mechanistic understanding from this investigation suggests that future searches for low-temperature SEG of Si could focus on SiH2R2 like precursors.

2D island nucleation controlled by nanocluster diffusion during Si and Ge epitaxy on Si(1 1 1)-(7 × 7) surface at elevated temperatures

We have studied two-dimensional (2D) island nucleation at the initial stages of Si and Ge epitaxial growth near monatomic steps and on wide (up to 10 μm) terraces on the Si(1 1 1)-(7 × 7) surface in 500–750 °C interval by in situ ultrahigh vacuum reflection electron microscopy (UHV REM) and ex situ atomic force microscopy (AFM). Concentration of 2D islands nucleated on the terraces and depletion zone width near the steps have been measured as functions of deposition rate and substrate temperature. We have shown that GeSi and Si nanoclusters are dominating diffusion species providing surface mass transport on the Si(1 1 1)-(7 × 7) surface during Ge and Si epitaxial growth at temperatures above 500 °C and 600 °C, respectively; the activation energy of GeSi nanocluster diffusion has been first estimated at 1.3–1.4 eV. The kinetics of 2D island nucleation and growth near the steps (both for Si and Ge epitaxy) and on the wide terraces (for Ge epitaxy) is limited by surface diffusion only, and critical nucleus consists of i ≫ 1 nanoclusters.