Epilayer Design Research Articles

Optimization of the Epilayer Design for the Fabrication of Doped GaN Planar Gunn Diodes

Optimization of the Epilayer Design for the Fabrication of Doped GaN Planar Gunn Diodes

New barrier layer design for the fabrication of gallium nitride-metal-insulator-semiconductor-high electron mobility transistor normally-off transistor

This paper reports on the fabrication of an enhancement-mode AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistor with a new barrier epi-layer design based on double Al0.2Ga0.8N barrier layers separated by a thin GaN layer. Normally-off transistors are achieved with good performances by using digital etching (DE) process for the gate recess. The gate insulator is deposited using two technics: plasma enhance chemical vapour deposition (sample A) and atomic layer deposition (sample B). Indeed, the two devices present a threshold voltage (V th) of +0.4 V and +0.9 V respectively with ΔV th about 0.1 V and 0.05 V extracted from the hysteresis gate capacitance measurement, a gate leakage current below 2 × 10−10 A mm−1, an I ON/I OFF about 108 and a breakdown voltage of V BR = 150 V and 200 V respectively with 1.5 µm thick buffer layer. All these results are indicating a good barrier surface quality after the gate recess. The DE mechanism is based on chemical dissolution of oxides formed during the first step of DE. Consequently, the process is relatively soft with very low induced physical damages at the barrier layer surface.

Low Voltage, High Optical Power Handling Capable, Bulk Compound Semiconductor Electro-Optic Modulators at 1550 nm

AlGaAs bulk electro-optic Mach–Zehnder modulators with low ${V_\pi }$ are reported. Epilayer design is an npin , which is shown to be equivalent to a pin . Measured ${V_\pi }$ is 1 V for 1 cm long electrode and this result agrees very well with the numerical modeling. Modulator capacitance remains constant and current through the device is negligible over a wide bias range. Lowest bandgap of the material in the active waveguide region is larger than twice the photon energy at 1550 nm, significantly reducing material absorption, including two-photon absorption. Modulator characteristics remain unchanged under coupled input optical powers approaching 160 mW. Low ${V_\pi }$ combined with high optical power handling capability make these devices suitable for analog photonic links.

Computational Modelling-Based Device Design for Improved mmWave Performance and Linearity of GaN HEMTs

In this work, a comprehensive, TCAD based design approach for mmWave (mmW) GaN HEMTs is presented. Unique trade-offs between epi-layer design and HEMT's mmW performance are discussed. Effect of surface states on cut off frequency is modeled and presented. We have found that carrier trapping by the donor type interface states causes RF performance drift at high drain fields, which particularly leads to the non-linear behavior of mmW HEMTs at high drain bias. Moreover, we have observed that channel electrostatics, barrier layer, and UID GaN channel design govern the linearity and scaling behavior of such GaN HEMTs. To improve channel electrostatics, which improves the linearity and cut-off frequency, a partially recessed barrier under the gate is studied. A relative study of AlN/GaN HEMT and AlGaN/GaN HEMTs is performed to investigate the nonlinearity behavior. In addition, the dependence of cut-off frequency on contact resistance and lateral scaling is studied for partially-recessed barrier and conventional design for both AlN and AlGaN barrier types. The mmW performance is found to be a strong function of barrier design in the gate and recess regions. Unique design trends and physical behavior was observed for AlN and AlGaN barriers, which signifies that design guidelines derived for one epi-stack can't be deployed to the other.

Doped Barrier Al0.65Ga0.35N/Al0.40Ga0.60N MOSHFET With SiO2 Gate-Insulator and Zr-Based Ohmic Contacts

This letter reports an Al0.65Ga0.35N-Al0.4Ga0.6N metal–oxide–semiconductor–heterojunction–field–effect–transistor (MOSHFET) with an SiO2 gate-insulator. For this first demonstration of an AlGaN channel MOSHFET, a new doped barrier epilayer design led to linear source–drain ohmic-contacts formed by Zr-based metal stack with a contact resistance as low as $1.64~\Omega \cdot \textsf {mm}$ . For a device with 6- $\mu \text{m}$ source–drain opening a record saturation current of 0.6 A/mm (at gate bias of 6V) was measured. In contrast to a conventional Schottky-gate HFET, the gate-oxide from the pulsed plasma enhanced chemical vapor deposition decreased the MOSHFET gate leakage current by a factor of 104 with only a 1.5-V shift in the threshold voltage. A drift mobility of 430 cm $^{2}/\textsf {V}\cdot \textsf {s}$ is measured at zero-gate bias, which increases to 800 cm $^{2}/\textsf {V}\cdot \textsf {s}$ close to the threshold voltage. The device characteristics up to 250°C are used to calculate the temperature dependence of the drift mobility.

Atomistic Approach for Modeling the Wafer Curvature for Pseudo-Morphic and Non-Pseudo-Morphic Epitaxial Multilayer Structures

During last few decades, there have been tremendous progress in the development of III-V based and III-Nitride based devices, namely High Electron Mobility Transistors (HEMT) and Light Emitting Diodes (LEDs). Research interest has recently shifted towards III-V compound semiconductor epitaxy on large diameter (200 mm) Si substrates in order to realize III-V-on-Si and CMOS integration. Due to large lattice and thermal mismatch between III-V and Si materials, e g. GaN-on-Si wafers experience large internal stresses and significant wafer bow. The wafer bow is severe for large wafers (for a given radius of curvature, the wafer bow increases by 125% for 150 mm and 300% for 200 mm diameter wafers compared to 100 mm wafers). This results in wafer fragility issues, as well as difficulties in subsequent handling and processing of such wafers. These issues are typically addressed using thicker Si substrates and careful design of buffer layers. While there are many experimental efforts to overcome these challenges, there are only limited reports that try to properly explain and understand the mechanism of wafer curvature. An appropriate theoretical model which predicts the final wafer curvature for given epilayer designs would greatly improve our ability to design optimal buffer and device layers. There are so far two main models for epitaxial multilayers which relate the wafer curvature to the strain state and the material properties of each layer. Ohlsen et al. (J. App. Phys. 1977) derived an analytical expression for the stress in each layer and the final wafer curvature for a given layer stack. This model however does require one to define strain states in each layer which is not straightforward to predict prior to the actual hetero-epitaxy of complex layers with large misfit dislocation densities such as in the GaN-on-Si system. Usher et al. (Phys. Rev. B 2003) proposed an atomistic approach for analyzing pseudo-morphic multi-layer structures, and were able to provide a closed form equation for radius of curvature. However, none of the reports have explicitly considered the thermal strain in the calculation. In this presentation we would address these limitations and provide a complete description of the wafer curvature including the effects of both lattice mismatch and coefficient of thermal expansion mismatch. We extend the atomistic approach to calculate the radius of curvature for non-pseudomorphic systems like III/V-on-Si systems. The density of misfit dislocations at each interface is used as a parameter to define the effective lattice constant of partially relaxed epilayers at the interface. Subsequently the lattice constant at any point in each layer is defined with respect to the interface lattice constant and is used to calculate the strain. Then the total strain energy of the resulting system is calculated as a function of system curvature, with the minimum energy solution corresponding to the predicted final curvature of the wafer. For better accuracy each epitaxial layer may be divided to separate sublayers with individual misfit dislocation density values. For illustration GaN-3xAlGaN-AlN-Si system was considered and radius of curvature was predicted. The accuracy of the model depends on the accuracy with which the misfit dislocation density is known. Experimental techniques like TEM and electron beam induced current (EBIC) can be used to estimate or quantify the number of dislocated atoms. Finally, we will include the thermal effect within the atomistic approach to be able to predict in-situ curvature of III/V-on-Si systems which will be helpful in designing the growth experiments for various devices.

High Electron Mobility Transistors With Al0.65Ga0.35N Channel Layers on Thick AlN/Sapphire Templates

We report Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.85</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.15</sub> N/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.65</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.35</sub> N high-electron mobility transistors on low-defect AlN buffer layers over basal plane sapphire substrates. A new epilayer design consisting of a doped barrier layer yielded sheet resistivity values as low as 1800 Ω/□. Devices with the source-drain spacing of 5.5 μm and a gate length of 1.8 μm exhibited peak drain-currents as high as 250 mA/mm at a gate bias of +4 V. We also show that the 3-μm thick low-defect AlN buffer layers over sapphire to provide sufficient thermal conduction which enables stable device operation up to at least 40 V at 250 mA/mm with no current droop.

Impact-ionization-engineered avalanche photodiode arrays for free-space optical communication

High-sensitivity photodetectors serve two purposes in free-space optical communication: data reception and position sensing for pointing, tracking, and stabilization. Two separate detectors are traditionally utilized to perform these tasks, but recent advances in the fabrication and development of large area, low-noise avalanche photodiode (APD) arrays have enabled these devices to be used both as position-sensitive detectors and communications receivers because of the conflicting performance criteria. Combining these functionalities allows for more flexibility and simplicity in optical assembly design without sacrificing the sensitivity and bandwidth performance of smaller, single-element data receivers. Beyond eliminating the need to separate the return beam into two separate paths, these devices enable implementation of adaptive approaches to compensate for focal plane beam wander and breakup, which is often seen in highly scintillated terrestrial and maritime optical links. While the Naval Research Laboratory and Optogration, Inc. have recently demonstrated the performance of single period, InAlAs/InGaAs APD arrays as combined data reception and tracking sensors, an impact-ionization-engineered epilayer design achieves even lower carrier ionization ratios by incorporating multiple multiplication periods engineered to suppress lower ionization rate carriers while enhancing the higher ionization rate carriers of interest. This work presents a three-period I2E concentric, five-element APD array rated for bandwidths beyond 1 GHz with measured carrier ionization ratios of 0.05 to 0.1 at moderate APD gains. The epilayer design of the device will be discussed along with initial device characterization and high-speed performance measurements.

Electrodes for wide-bandwidth substrate-removed electro-optic modulators

This Letter is on wide-bandwidth electrodes suitable for ultralow voltage substrate-removed compound semiconductor electro-optic modulators. Using a loaded line approach, traveling wave electrodes suitable for wide-bandwidth and low-voltage operation were studied theoretically and experimentally up to 35 GHz. Using staircase waveguides and n-i-p-i-n epilayer designs, electrode capacitance and resistance were reduced significantly. Experimental and modeling results are found to agree very well. Theoretical and experimental results indicate that subvolt modulators with electrical to optical bandwidths in excess of 30 GHz are possible.

Output Power Limitations and Improvements in Passively Mode Locked GaAs/AlGaAs Quantum Well Lasers

We report a novel approach for increasing the output power in passively mode locked semiconductor lasers. Our approach uses epitaxial structures with an optical trap in the bottom cladding that enlarges the vertical mode size to scale the pulse saturation energy. With this approach we demonstrate a very high peak power of 9.8 W per facet, at a repetition rate of 6.8 GHz and with pulse duration of 0.71 ps. In particular, we compare two GaAs/AlGaAs epilayer designs, a double quantum well design operating at 830 nm and a single quantum well design operating at 795 nm, with vertical mode sizes of 0.5 and 0.75 μm, respectively. We show that a larger mode size not only shifts the mode locking regime of operation towards higher powers, but also produces other improvements in respect of two main failure mechanisms that limit the output power: the catastrophic optical mirror damage and the catastrophic optical saturable absorber damage. For the 830 nm material structure, we also investigate the effect of non-absorbing mirrors on output power and mode locked operation of colliding pulse mode locked lasers.

Reduction of Turn-on, Knee, and Offset Voltages of InAlGaP/GaAs HBTs Using $\delta$-Doping in the InAlGaP Emitter

In0.5(Al0.3Ga0.7)0.5P/GaAs heterojunction bipolar transistors (HBTs) are demonstrated as an alternative to AlGaAs/GaAs and InGaP/GaAs HBTs for microwave applications. The effects of δ -doping in the InAlGaP emitter on both electron transport and transistor performance are systemically explored. For comparison, a reference HBT with an identical epilayer design to that of the δ-doped HBT, except for the absence of a δ-doping layer, is processed at the same time. The two design options are established to yield comparable dc current gains β . InAlGaP can be selectively etched over GaAs, making the device etching routine. Notably, δ-doping simultaneously reduces the knee voltage Vknee, the offset voltage Voffset, and the turn-on voltage VBE, on of the HBTs of interest. This paper also sheds light on the behavior of the offset voltage for these devices. An unexpected attribute of the investigated devices is the effect of the base current on the offset voltage. The offset voltage is analyzed using a modified large-signal model. A further important inference of this paper is that the β of the transistor is flat across a large range of currents at room temperature. The use of InAlGaP as the emitter layer substantially decreases the variation of β with substrate temperature in the HBTs. The stability of the dc current gain with varying temperature is attributable to the inherent characteristics of this material system. The results make InAlGaP/GaAs δ-HBTs viable contenders for millimeter-wave application.

Exploration of the inherent magnetoresistance in InSb thin films

The depth-dependent electrical properties of InSb thin films grown on GaAs substrates result in an inherent magnetoresistance in the layers. For certain applications it is important to be able to manipulate this effect controllably. This paper demonstrates both experimentally and theoretically that the magnitude of the magnetoresistance can be dramatically changed by epilayer design. We show that the inclusion of a doped region in part of the layer structure allows the inherent magnetoresistance to be changed by a factor of 40.

Spectroscopic characterization of 1450 nm semiconductor pump laser structures for Raman amplifiers

In order to characterize various different epilayer designs for semiconductor Raman amplifier pump lasers, combined electromodulated reflectance (ER) and photoluminescence (PL) studies were performed on wafer samples of InP / InGaAsP / InGaAsP edge-emitter laser structures in the infrared spectral region. Information about the quantum well (QW) transitions is obtained primarily from the ER, with additional corroboration provided by the PL. The ER spectra are fitted with a line shape model to obtain the ground-state and higher-order QW transition energies, which are found to agree well with theoretically calculated values. The ER spectra also provide the waveguide core and barrier compositions and built-in electric fields in the laser structures. The information provided by ER studies on the prefabrication wafers is found to corroborate well with diagnostic spontaneous emission measurements performed on actual laser devices fabricated from the same wafer batches.

Ultraviolet light-emitting diodes at 340 nm using quaternary AlInGaN multiple quantum wells

An ultraviolet light-emitting diode with peak emission wavelength at 340 nm is reported. The active layers of the device were comprised of quaternary AlInGaN/AlInGaN multiple quantum wells, which were deposited over sapphire substrates using a pulsed atomic-layer epitaxy process that allows precise control of the composition and thickness. A comparative study of devices over sapphire and SiC substrates was done to determine the influence of the epilayer design on the performance parameters and the role of substrate absorption.

Quaternary AlInGaN MQWs for Ultraviolet LEDs

AbstractWe report a pulsed atomic layer epitaxy (PALE) growth technique for quaternary AlInGaN films for ultraviolet optoelectronic applications. Using the PALE approach high quality quaternary AlInGaN/AlInGaN multiple quantum wells (MQWs) were successfully grown over sapphire substrates. From X-ray diffraction, atomic force microscopy, and photoluminescence study, a high structural and optical quality was established for the AlInGaN MQWs. Incorporating the PALE grown quaternary MQWs as the active layer of light emitting diode (LED) on sapphire or SiC substrates we also demonstrated room temperature deep ultraviolet electroluminescence under dc and pulsed electrical pumping. The peak emission wavelength can be tuned from 305 nm to 340 nm with spectrum FWHM of about 20 nm by varying the alloy compositions of the quaternary AlInGaN active layers using PALE. Comparative study of LEDs over sapphire and SiC substrates was also done in order to determine the influence of epilayer design on the performance parameters and the role of the substrate absorption.

Linearity characteristics of GaAs HBTs and the influence of collector design

The linearity characteristics of GaAs heterojunction bipolar transistors (HBTs) are studied through measurement and analysis. Third-order intermodulation distortion behavior of HBTs is examined on devices with various epilayer designs and at various bias points, loads, and frequencies. Calculations from an analytical model reveal a strong bias and load dependence of third-order intercept point (IP3) on the nonlinearities from transconductance and the voltage dependence of base-collector capacitance. However, a simple model is not able to predict the fine details of IP3 with bias. A large-signal HBT model with an accurate description of the base-collector charge is shown to account for the measured trends. The base-collector charge function accounts for the modulation of base-collector capacitance with current, electron velocity modulation, and the Kirk effect (base pushout) for GaAs-based HBTs. A detailed study of the influence of collector design on linearity is also presented.

Bipolar transistor epilayer design using the MAIDS mixed-level simulator

In this paper, we address the epilayer design of the bipolar transistor using the one-dimensional (1-D) mixed-level simulator MAIDS (microwave active integral device simulator). MAIDS facilitates simulation of the electrical behavior of bipolar (hetero) junction transistors with various doping profiles and under different signal conditions in a realistic circuit environment. MAIDS as implemented within Hewlett Packard's microwave design system is a useful and promising tool in the development of bipolar transistors for large-signal conditions. Using MAIDS, we have identified the dominant bipolar transistor distortion sources with respect to the biasing conditions. Simulation results are compared with small- and large-signal measurements for the BFQ135 transistor, which has been developed for cable television (CATV) applications. By analyzing the measured and simulated data, we have developed an optimum epilayer design map for third-order intermodulation distortion that has proven to be particularly useful in the epilayer dimensioning of transistors for CATV applications.

Impact of InP HEMT epilayer designs on side gating effects

The hole flow to the gate due to the impact ionization mechanism developping in the HEMT GaInAs channel is demonstrated to be reduced by a specific epilayer design: the insertion of a high bandgap hole barrier. However, this improvement leads to drain current transients strongly governed by the side gate bias.

Monolithic integration of In 0.2 Ga 0.8 Asvertical-cavity surface-emitting lasers with resonance-enhanced quantum well photodetectors

Vertical-cavity surface-emitting lasers (VCSELs) have been monolithically integrated with resonance-enhanced photo-detectors (REPDs) using a single epilayer design, to produce a simple array of sources and detectors for optical interconnect applications. The detectors, which contain a three quantum well InGaAs absorption region, achieve quantum efficiencies as high as 85%, and the VCSELs achieved threshold current densities as low as 850 A/cm2 and differential quantum efficiencies as high as 50%.

Integrable surface-emitting laser-based optical switches and logic gates for parallel digital optical computing

We describe the recent advances in a monolithic optoelectronic technology based on the integration of two-dimensional arrays of cascadable optical switches and optical logic gates consisting of vertical-cavity surface-emitting lasers (VCSEL's) and heterojunction phototransistors or photothyristors. Different combinations of these components can perform optical switching, logic, memory, and regeneration. Latching, nonlatching, and bistable switches with high optical gain and contrast are demonstrated by using a single GaAs-AlGaAs epilayer design along with single-stage Boolean optical logic functions: AND, OR, IDENTITY, INVERT, NAND, NOR, and XOR. As an application to parallel, digital arithmetic logic, we describe a simple, compact, two-chip binary adder, which uses optical symbolic substitution and two-dimensional VCSEL-PNPN logic gate arrays.