Epi Process Research Articles

Lateral scaling challenges for SiGe NPN BiCMOS process integration

Lateral scaling was employed to achieve high-speed NPN bipolar performance, and specifically the role of active scaling was investigated. As function of active design rule over-plot emitter window, two collector implant designs are compared in a self-aligned emitter integration scheme. Decreasing design rule significantly decreases collector-base capacitance as a result of greater isolation from the extrinsic base. Non-selective SiGe epi process integration is susceptible to deleterious facet growth at the active edge, which can compromise the base resistance and negate any overall F max gain. An optimization of design rule and fabrication are presented for nominal 200 GHz F t devices; the F max gain was improved from 165 to 215 GHz. Normal DC output characteristics and a BV ceo of 2.4 V facilitate modular integration within 1.2 or 1.8 V core BiCMOS technology nodes.

Quantification of Ge and B in SiGe using secondary ion mass spectrometry

This paper reports on routine secondary ion mass spectrometry (SIMS) applications in SiGe EPI process control. Subjects, among others, are quantitative Ge and B co-dopant depth profiles because of their importance for device performance. SIMS depth profiling with oxygen primary ions at normal incidence gives superior depth resolution, whereas Cs sputtering allows arsenic and oxygen monitoring. An intrinsic method to compensate erosion rate variations with Ge-content is proposed.

Technological aspects of oxidated porous silicon waveguides

Technological aspects related to the fabrication of buried oxidized porous silicon waveguides (OPSWG) as the influence of swirl defects and a suitable epitaxial method to bury OPSWG have been investigated. The influence of swirl defects on OPSWG performances is presented. The formation of a non-homogeneous porous silicon, caused by swirl defects, results in an incomplete oxidation and in an increase of optical loses. The idea of burying waveguides has been tested by a suitable epi process covering using dichlorosilane and silane as reacting gases. The paper presents and discusses the preliminary results. In this paper, are presented the technological studies related to the fabrication of buried OPSWG: (i) swirl defects influence on the structure and on the guiding properties of OPSWG; (ii) epitaxial deposition process suitable for the realization of defects free silicon layer over the OPSWG.

Applications and processing of SiGe and SiGe:C for high-speed HBT devices

The continued growth of high-speed-digital data transmission and wireless communications technology has motivated increased integration levels for ICs serving these markets. Further, the increasing use of portable wireless communications tools requiring long battery lifetimes necessitates low power consumption by the semiconductor devices within these tools. The SiGe and SiGe:C materials systems provide solutions to both of these market needs in that they are fully monolithically integratible with Si BiCMOS technology. Also, the use of SiGe or SiGe:C HBTs for the high-frequency bipolar elements in the BiCMOS circuits results in greatly decreased power consumption when compared to Si BJT devices. Either a DFT (graded Ge content across the base) or a true HBT (constant Ge content across the base) bipolar transistor can be fabricated using SiGe or SiGe:C. Historically, the graded profile has been favored in the industry since the average Ge content in the pseudomorphic base is less than that of a true HBT and, therefore, the DFT is tolerant of higher thermal budget processing after deposition of the base. The inclusion of small amounts of C (e.g. <0.5%) in SiGe is effective in suppressing the diffusion of B such that very narrow extremely heavily doped base regions can be built. Thus the f T and f max of a SiGe:C HBT/DFT are capable of being much higher than that of a SiGe HBT/DFT. The growth of the base region can be accomplished by either nonselective mixed deposition or by selective epitaxy. The nonselective process has the advantage of reduced complexity, higher deposition rate and, therefore, higher productivity than the selective epitaxy process. The selective epi process, however, requires fewer changes to an existing fabrication sequence in order to accommodate SiGe or SiGe:C HBT/DFT devices into the BiCMOS circuit.

An anti-snapback circuit technique for inhibiting parasitic bipolar conduction during EOS/ESD events

In this work, an anti-snapback circuit technique called source injection (SI) is presented for the first time ever, which is shown to inhibit parasitic bipolar conduction during EOS/ESD events. The design is presented for a fully salicided, 0.25 μm, 35 Å /70 Å dual gate oxide, thin-epi, retrograde n-well, bulk CMOS technology. The technique is shown to greatly extend the snapback voltage of NMOS devices in this technology, which are usually destroyed instantaneously once snapback occurs. The design also has the benefit of controlling output buffer impedances for impedance matching to transmission-line loads. The design is fully compatible with the baseline process and has been shown to increase ESD robustness for positive discharge stress modes, which are the most difficult to protect for in epi processes. An increase of >1.5 kV is demonstrated for HBM, an increase of 550 V is shown for MM, and an increase of >550 V is exhibited for CDM, over non-SI and SI iopad designs, respectively.

Use of narrow collector layers in Si and Si 1− xGe x bipolar transistors

This paper describes the use of narrow collector layers in planar LOCOS isolated Si and SiGe bipolar transistors. The transistors have been fabricated using either a single or double epi process in order to compare the doping control in the collector layer. In contrast with the conventional double epi process, in the single epi process, the collector, base and emitter layers were all deposited in one single step after the high thermal budget LOCOS process. We show that the single epi process minimises dopant outdiffusion from the n + buried subcollector, thus offering the potential of submicron low doped collector and the benefit of reduced epitaxy cost. Attention is drawn to the leakage current in the base–collector junction when intersecting the poly-Si/Si deposited at the oxide window edge.

Wafer Characterization of an Epi Reactor Using Sheet Resistance Mapping

AbstractSheet resistance mapping has become an indispensable tool in characterizing ion implanters for both integrated circuit manufacturers and equipment manufacturers. The sheet resistance mapping technique is now being extended into additional applications such as the characterization of metal deposition, CVD, and epitaxial silicon growth. This technique has become especially necessary with the advent of 150mm and 200mm wafers, where 5 or 9 site measurements cannot provide sufficient data essential for process control.In order to optimize the performance of an epi reactor it is necessary to control and characterize the gas flows and temperature distributions inside the reactor. The control of these variables is essential for thickness and resistivity uniformity in epi layers. This paper describes the use of sheet resistance profiles and contour maps to study the resistivity and thickness uniformity variations in an epi reactor. The sheet resistance maps allow for control of the epi process without requiring data from other test sources.This ensures real time process control for production, as well as very rapid feedback for maintenance while doing equipment repair.