Hole Mobility Enhancement Research Articles

Ultrathin Ge-on-Insulator Metal Source/Drain p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated By Low-Temperature Molecular-Beam Epitaxy

We demonstrate the enhancement of hole mobility in an ultrathin Si/Ge/Si-on-insulator (SOI) channel metal–oxide–semiconductor field-effect transistor (MOSFET) with a metal source and drain (S/D). The ultrathin Si/Ge structure is fabricated on a SOI substrate by low-temperature molecular-beam epitaxy (LTMBE). We examined the impact of the Si/Ge/Si structural parameters and the crystal quality on the electrical characteristics of MOSFETs, particularly from the viewpoints of the Ge thickness and the annealing temperature. As a result, the hole mobility of the fabricated Ge-on-insulator (GOI)-pMOSFETs after annealing at 600 °C was found to be 1.2 times larger than the Si universal hole mobility. For the Ge thickness dependence of hole mobility, the MOSFETs with the Ge thicknesses of 8, 12, and 16 nm had almost the same mobility. On the other hand, the sample with 4 nm Ge thickness had lower mobility. For the annealing temperature dependence, the hole mobility had a maximum value at 600 °C and decreased with increasing annealing temperature above 700 °C.

Influence on Hole and Electron Mobilities of Using a Multi-Wall Structural Channel Metal–Oxide–Semiconductor Field-Effect Transistors

We investigated the influence on hole and electron mobilities of metal–oxide–semiconductors field-effect transistors with a multi-wall channel structure. Though electron mobilities are decreased, using a multi-wall channel structure enhances hole mobilities. We prepared samples with various wall-heights, widths and wall-pitches. The multi-wall channel structure produces a (110) surface channel and a strain produced by polycrystalline silicon gates. These enhance the hole mobility. The degree of hole mobility enhancement depends on the wall-height and wall-pitches. We also investigated the influence of bi-axial strain in the substrate on the multi-wall structure by using strained-Si substrate.

Characteristics of strained-germanium p- and n-channel field effect transistors on a Si (1 1 1) substrate

Characteristics of strained-germanium (Ge) p- and n-channel field effect transistors directly on Si (1 1 1) substrates have been investigated. A strained-Ge layer with a thickness of ∼4 nm has been grown on the relaxed Si/Si (1 1 1) substrate by ultra-high-vacuum chemical vapour deposition. To improve the oxide/strained-Ge interface, a thin Si-cap layer with a thickness of 3 nm has been grown on the strained-Ge layer. After the device process, 1 nm thickness of Si-cap layer remains on the strained-Ge layer. Thicknesses of all epitaxial layers have been measured by transmission electron microscopy. Raman spectroscopy measurement on the Si-cap/strained-Ge layer shows that the strained-Ge layer has a compressive strain of ∼1.25%. A hole confinement shoulder on the capacitance–voltage curve at the accumulation region has been observed due to carrier confinement at the Si-cap/strained-Ge hetero-interface. A metal–oxide–semiconductor (MOS) structure on the strained-Ge layer shows a moderate interface trap charge density of ∼2.8 × 1011 cm−2 eV−1. Strained-Ge p- and n-channel field effect transistors show low off-state leakage currents of ∼3.8 × 10−13 A µm−1 and ∼6.5 × 10−13 A µm−1, respectively. Drive currents of strained-Ge p- and n-channel field effect transistors are enhanced by ∼100% and ∼40%, respectively, as compared with bulk Si (1 1 1) transistors. Peak hole and electron mobility of strained-Ge (1 1 1) field effect transistors at the low effective field are found to be ∼110% and ∼30% enhancement, respectively, as compared with bulk Si (1 1 1) transistors, due to high hole and electron mobility enhancement factor as well as strain-induced lower conduction mass in the strained-Ge channel.

Hole Mobility and Thermal Velocity Enhancement for Uniaxial Stress in Si up to 4 GPa

A theoretical study of the response of hole mobility and thermal velocity, both relevant for short channel devices, to [110] uniaxial stress in Si up to 4 GPa of both tension and compression has been conducted. The strained-Si bandstructure was calculated using the kmiddotp method. Effective masses, thermal velocities, and scattering rates were calculated from the bandstructure as a function of stress. Mobilities were then calculated via full band Monte Carlo simulations. Calculated mobilities match experimental and theoretical data from prior work addressing lower degrees of stress. Large increases in both carrier thermal velocities and mobilities were found. In the high-stress regime between 1 and 2 GPa, mobilities exhibit a strong superlinear dependence, and compressive stress becomes more favorable for increasing both mobilities and thermal velocities in pMOS. Improvements in both thermal velocity and mobility finally only begin to rolloff toward apparent saturation as we push the stress toward 4 GPa in these simulations

Interrupted Mg doping of GaN with MOCVD for improved p-type layers

Uniformity doping, δ-doping and growth-interruption doping to produce gallium nitride (GaN): Mg has been investigated by low-pressure metal-organic chemical vapor deposition (LP-MOCVD). It was demonstrated by electrical, optical, and surface studies that films produced by growth-interruption-Mg-doping produce the best crystal quality, this doping method increasing self-compensation because of the incorporation of additional impurities during the interruption period. Mg- δ-doping employs GaN:Mg/UGaN superlattices valence band edge oscillation to enhance hole concentration leading to significantly reduced p-type resistivity, enhanced hole mobility. This doping method also leads to improved surface morphology.

Hole mobility enhancement of Si0.2Ge0.8 quantum well channel on Si

The ultrathin strained Si0.2Ge0.8 quantum well channel (∼5nm) directly grown on Si substrates is demonstrated with low defect density and high hole mobility. The quantum well Si0.2Ge0.8 channel reveals an ∼3.2 times hole current enhancement and an ∼3 times hole mobility enhancement as compared with the bulk Si channel. The output current-voltage characteristics under the external mechanical strain confirm the compressive strain in the channel. The external compressive strain further enhances the hole mobility in a Si0.2Ge0.8 channel.

Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions

We explore several technology options for the enhancement of electron and hole mobility in complementary metal–oxide–semiconductor (CMOS) field-effect transistors, focusing on strain engineering using lattice-mismatched source/drain (S/D) materials. Silicon–carbon (Si1−yCy) and silicon–germanium (Si1−xGex) have lattice constants different from that of the Si channel. When Si1−yCy or Si1−xGex is embedded in the transistor S/D region, lateral tensile or compressive strain is induced in the adjacent Si channel, leading to improvement in the electron or hole mobility, respectively. The origin of the strain effect, process integration, device characteristics and strain enhancement approaches are discussed.

Enhancement of hole conductance in the Ge quantum well of a SiGe heterostructure via realization of double-side modulation doping

Proper realization of double-side modulation doping resulted in a significant enhancement of two-dimensional hole gas (2DHG) conductance up to 9.1 mS in the compressive strained 8 nm thick Ge quantum well (QW) of a SiGe heterostructure. This was mainly achieved due to around two times enhancement of 2DHG Hall mobility up to 30 000 cm2 V−1 s−1 and sheet carrier density up to 1.9 × 1012 cm−2 at 3 K. By employing this way of modulation doping, the hole's wavefunction was moved away from the interface towards the centre of Ge QW that allowed the enhancement of hole mobility. The observed increase of carrier density was due to the transformation of a triangular-like Ge QW energy profile into a rectangular-like one.

Strained SOI/SGOI dual-channel CMOS technology based on the Ge condensation technique

Ge-rich strained SiGe-on-insulator (SGOI) pMOSFETs were fabricated by oxidizing strained SiGe layers on SOI substrates at high temperatures. It was found that strain was accumulated in the SGOI channels during this process, called Ge condensation, associated with the increase in the Ge fraction. Significant hole-mobility enhancements up to a factor of 10 were observed due to the high Ge fractions over 0.5 and large strain values over 1%. The SGOI pMOSFETs were also co-integrated with strained SOI nMOSFETs or ultra-thin SOI nMOSFETs to form dual-channel CMOS devices. The dual-channel structures were fabricated by conventional CMOS processes combined with the Ge condensation process and selective epitaxial growth processes. High hole mobility was observed in the SGOI pMOSFETs of the CMOS devices, whereas an enhancement or no degradation of electron mobility was observed in the strained or the unstrained SOI nMOSFETs. Based on the measured carrier mobility of the long-channel nMOSFETs and pMOSFETs, short-channel CMOS performance enhancement of around 30% was estimated.

Influence of Strained Si1-yGey Layer Thickness and Composition on Hole Mobility Enhancement in Heterostructure p-MOSFETs with Ge Contents y from 0.7 to 1.0

Hole mobility enhancements of 5 to 8X are demonstrated in heterostructure p-MOSFETs for strained Si1-yGey fractions, y ranging from 0.8 to 1. The influence of SiGe film thickness on hole mobility for strained Si0.3Ge0.7-channel p-MOSFETs is also investigated. Mobility is found to decrease significantly for channel thicknesses below 7 nm. Off-state leakage increases exponentially with increasing Ge concentration in the channel. Temperature dependent measurements of the leakage are consistent with trap-assisted tunneling at low drain-to-gate bias, and with band-to-band tunneling at higher biases. A reduction in leakage is observed for SiGe channel layer thicknesses below 7 nm. The results presented in this work are relevant to modeling and optimization of the performance of high mobility, high Ge concentration strained heterostructure p-MOSFETS.

High Mobility Strained Ge / SiGe PMOSFETs for High Performance CMOS

Dramatic hole mobility enhancement of 4-25X has been demonstrated in compressively strained Ge p-channel MOSFETs - the highest mobility enhancement for hole carriers among all available options. This paper reviews the material properties of strained Ge/SiGe and the integration challenges of strained Ge MOSFETs. A compatible process to incorporate high performance strained Ge PMOSFETs into standard CMOS technology is presented.

Laser Spike Annealing of Strained Si/ Strained Si0.3Ge0.7/ Relaxed Si0.7Ge0.3 Dual Channel High Mobility p-MOSFETs

Sub-melt temperature laser spike annealing is investigated as a low thermal budget solution for source/drain annealing in strained Si/ strained Si0.3Ge0.7/relaxed Si0.7Ge0.3 dual channel p-MOSFETs. A constant hole mobility enhancement factor of 4x is maintained relative to Si control MOSFETs, for laser annealing temperatures up to approximately 1000ºC. This temperature is significantly higher than possible with rapid thermal annealing, due to device degradation associated with Ge diffusion during rapid thermal annealing. Mobility is found to decrease dramatically in the heterostructure MOSFETs for laser annealing temperatures above ~ 1000ºC. SIMS analysis shows very little Ge diffusion, even for an 1100ºC laser anneal. Capacitance-voltage analysis and Raman spectroscopy suggest that there is some strain relaxation for the 1100ºC anneal. Transmission electron microscopy analysis indicates localized strain variation and defects on the order of 107 cm-2 for the heterostructure MOSFET subject to laser annealing at 1100ºC. The mobility degradation for LSA temperatures above ~ 1000ºC is consistent with a combination of strain relaxation and scattering from defects.

Hole mobility enhancement of p-MOSFETs using global and local Ge-channel technologies

Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, we review our recent results on high hole mobility p-MOSFETs using global/local SiGe or Ge channels. There are two directions for introducing SiGe or Ge channels into Si CMOS platform. One is to use SiGe or Ge global substrates and the other is to form SiGe or Ge-channel regions locally on Si wafers. In both cases, the Ge condensation technique, where Ge-channel layers are formed by oxidizing SiGe films on SOI substrates, are effectively utilized. As for the global technologies, ultrathin GOI substrates are prepared and used to fabricate high mobility GOI p-MOSFETs. As for the local technologies, SGOI or GOI channels are formed locally in the active area of p-MOSFETs on SOI wafers. It is shown that the hole mobility enhancement factor of as high as 10 is obtained in locally fabricated p-MOSFETs through the effects of high-Ge content and the compressive strain. Furthermore, the local Ge-channel technologies are combined with global SiGe or Ge substrates for pursuing the optimal and individual design of n-MOSFETs and p-MOSFETs on a single Si wafer. The CMOS device composed of strained-Si n-MOSFETs and SGOI p-MOSFETs is successfully integrated on a same wafer, which is a promising CMOS structure under deep sub 100 nm technology nodes.

Enhancement of hole injection in pentacene organic thin-film transistor of O2 plasma-treated Au electrodes

The effect of oxygen plasma treatment on enhancement of hole mobility was demonstrated using pentacene organic thin-film transistors (OTFTs) with bottom-contact Au electrodes. Linear field-effect mobility increased from 3.2×10−2to7.4×10−2cm2∕Vs as the Au electrodes were treated with O2 plasma. Secondary electron emission spectra revealed that the work function of oxygen plasma-treated Au is 0.5eV higher than that of untreated Au. This led to a reduced hole injection barrier at the interface of Au with pentacene, increasing the field-effect mobility of OTFTs.

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4μm have the drain current of 9.5μA/μm and the transconductance of 14μS/μm at Vgs−Vth=Vds=−1V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.

Influence of Strained Si1-yGey Layer Thickness and Composition on Hole Mobility Enhancement in Heterostructure p-MOSFETs with Ge Contents y from 0.7 to 1.0

not Available.

Enhancement of hole mobility and carrier density in Ge quantum well of SiGe heterostructure via implementation of double-side modulation doping

A significant improvement of transport properties of two-dimensional hole gas (2DHG) in the strained Ge quantum well (QW) of SiGe heterostructure was obtained via implementation of double-side modulation doping from bottom and top sides of Ge QW. Around two times enhancement of 2DHG Hall mobility up to 30000cm2V−1s−1 and sheet carrier density up to 1.9×1012cm−2 were obtained at 3K. By employing this way of modulation doping hole’s wave function was moved away from the interface towards the center of Ge QW that allowed enhancement of hole mobility due to reduction of interface roughness scattering.

PMOSFET with 200% mobility enhancement induced by multiple stressors

Recessed Si/sub 0.8/Ge/sub 0.2/ source/drain (S/D) and a compressive contact etch-stop layer have been successfully integrated resulting in nearly 200% improvement in hole mobility. This is the largest reported process-induced hole mobility enhancement to the authors' knowledge. This letter demonstrates that a drive-current improvement from recessed Si/sub 0.8/Ge/sub 0.2/ plus the compressive nitride layer are in fact additive. Furthermore, it shows that the mobility enhancement is a superlinear function of stress, leading to larger than additive gains in the drive current when combining several stress sources.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.

Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs

The combination of channel mobility-enhancement techniques such as strain engineering with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future technology nodes. The tradeoff between transport enhancement and OFF-state leakage current is compared experimentally for UTB MOSFETs in two types of materials: 1) strained Si directly on insulator (SSDOI) and 2) strained Si/strained Si/sub 1-z/Ge/sub z/ (z=0.46-0.55)/strained Si heterostructure-on-insulator (HOI). SSDOI of moderate strain level (e.g. /spl sim/ 0.8%) yields high electron-mobility enhancements for all electron densities, while high strain levels (e.g. /spl sim/ 1.6%) are required to obtain hole-mobility enhancements at high inversion charge densities. HOI is demonstrated to have similar electron-mobility characteristics to SSDOI, while hole mobilities are improved and can be maintained at high inversion charge densities. Hole mobility in strained channels with thickness below 10 nm is studied and compared for SSDOI and HOI. As the channel thickness is reduced, mobility decreases, as in unstrained silicon-on-insulator (SOI), though hole-mobility enhancements are demonstrated into the ultrathin-channel regime. Increased OFF-state leakage currents are observed in HOI compared to SSDOI and SOI. For a 4-nm-thick buried SiGe layer, leakage is reduced relative to devices with thicker SiGe channels.