Enhancement-mode Gallium Nitride Research Articles

Modelling and mitigating oscillation in E-mode GaN HEMT: A simulation-based approach to parasitic inductance optimization

The escalating demands in energy conversion necessitate the evolution of efficient power electronic devices beyond the limitations of traditional silicon (Si) counterparts. This research delves into the intricacies of the Enhancement mode Gallium Nitride High Electron Mobility Transistor (E-mode GaN HEMT). A focus is placed on its static characterization, parameter analysis, and the influence of external parasitic inductances, particularly regarding oscillation challenges during its hard switching process. Forward and revise bias are conducted through comparison with Si-MOSFET and Cascade-GaN HEMT, along with its static on-resistance and transfer characteristics. Through rigorous half-bridge double pulse circuit LTSPICE simulations, this study deciphers the turn-on and turn-off dynamics of the E-mode GaN HEMT. By scrutinizing various parasitic inductances, the research elucidates mechanisms instigating high-frequency voltage and current oscillations. Significantly, the research presents a hierarchy of parasitic inductance influences, employing an energy loss comparison. This analysis underscores the prominent impact of the common source parasitic inductance, which exhibits energy loss increases of 23.6 % and 22.7 % at junction temperatures of 25 °C and 75 °C, respectively. Building on these insights, the study recommends strategies to mitigate the effects of external parasitic inductance, underscoring the pivotal role of oscillation suppression in advanced GaN Printed Circuit Board (PCB) and Integrated Circuit (IC) designs. This comprehensive inquiry provides a blueprint for enhancing GaN circuit designs, paving the way for their optimal application in the evolving realm of power electronics.

Characterization of GaN HEMTs' Aging Precursors and Activation Energy Under a Wide Range of Thermal Cycling Tests

In this paper, 650 V / 7.5 A rated enhancement-mode (E-mode) Gallium Nitride (GaN) high-electron-mobility-transistors (HEMTs) with integrated gate drivers are characterized under thousands of accelerated thermal cycles (ATC) at different junction temperature stresses. This research helps in developing fundamental insights into GaN HEMTs' aging characteristics through the degradation of ten devices under ATC tests. For over 20,000 thermal cycles, the forward and reverse conduction losses, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> GSS, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> oss, and the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RDS</i> on are experimentally measured to identify the parameter shifts and the corresponding precursors. Results indicate that both <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IGSS</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> oss do not deviate much, but the values of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RDS</i> on, the forward and reverse conduction losses vary considerably with device aging. This paper also presents an empirical method to estimate the correlation between the acceleration factors of the GaN FETs' degradation process and the thermal cycling conditions. The value of the activation energy of the tested GaN HEMT devices is also derived using the empirical equations to be about 1.13 eV under the applied stress factors. This study finds that the degradation process of GaN HEMTs with age facilitates a reasonable correlation with different failure mechanisms, which further helps in reliability improvement.

EMI Mitigation of GaN Power Inverter Leg by Local Shielding Techniques

This paper presents local shielding techniques applied to a half-bridge inverter leg with the aim to reduce the common mode (CM) current noise at converter's DC input. The research study is conducted for 650V Enhancement mode Gallium Nitride (GaN) power transistor switches. Main contributors of parasitic capacitances referred to the inverter-leg middle point node are identified. Then, shielding solutions are proposed to reduce CM current emission by these capacitances. Respecting the precautions concerning the isolation of CM currents of the half-bridge inverter leg, the electromagnetic compatibility measurement setup is developed. Experimental step-by-step addition of local shielding copper layers to different contributors of middle point capacitance shows progressive attenuation of CM noise spectra.

Study of Self-Heating and High-Power Microwave Effects for Enhancement-Mode p-Gate GaN HEMT.

The self-heating and high-power microwave (HPM) effects that can cause device heating are serious reliability issues for gallium nitride (GaN) high-electron-mobility transistors (HEMT), but the specific mechanisms are disparate. The different impacts of the two effects on enhancement-mode p-gate AlGaN/GaN HEMT are first investigated in this paper by simulation and experimental verification. The simulation models are calibrated with previously reported work in electrical characteristics. By simulation, the distributions of lattice temperature, energy band, current density, electric field strength, and carrier mobility within the device are plotted to facilitate understanding of the two distinguishing mechanisms. The results show that the upward trend in temperature, the distribution of hot spots, and the thermal mechanism are the main distinctions. The effect of HPM leads to breakdown and unrecoverable thermal damage in the source and drain areas below the gate, while self-heating can only cause heat accumulation in the drain area. This is an important reference for future research on HEMT damage location prediction technology and reliability enhancement.

A Comprehensive Analytical Switching Transients and Loss Modeling Approach with Accurate Parasitic Parameters for Enhancement-Mode Gallium Nitride Transistors

A Comprehensive Analytical Switching Transients and Loss Modeling Approach with Accurate Parasitic Parameters for Enhancement-Mode Gallium Nitride Transistors

Packaging and high-temperature characterization of a 650 V, 150 A eGaN HEMT

Among the salient features of gallium nitride (GaN) power semiconductor devices is their high-temperature capability. However, commercial GaN devices, such as the high-electron-mobility transistors (HEMTs), are limited to 125 °C junction-temperature operation because of their packaging. To explore the high-temperature capability of GaN power devices, a commercial 650 V, 150 A enhancement-mode GaN HEMT chip was packaged by silver-sintering die-bonding on direct-bond-copper substrate and encapsulation in a high-temperature polymer enclosure filled with nitrogen. Static characteristics of the packaged GaN device were measured at temperatures up to 250 °C. The threshold voltage of the transistor at 250 °C decreased to around 0.9 V, about 30% lower than that at room temperature. At temperatures beyond 150 °C, the saturation current fell sharply below the rated current, resulting in a rapid rise in the on-resistance versus current. At 250 °C, the saturation current decreased rapidly to around 67 A, <45% of the rated current. The reverse leakage also increased sharply at temperatures beyond 150 °C. Although the packaged device was operational at 250 °C, one would need to significantly lower the expectations for its performance and address the challenges of packaging and thermal management if it were to be used in a high-temperature power converter.

Analysis and Characterization of Normally-Off Gallium Nitride High Electron Mobility Transistors

High electron mobility transistor (HEMT) based on gallium nitride (GaN) is one of the most promising candidates for the future generation of high frequencies and high-power electronic applications. This research work aims at designing and characterization of enhancement-mode or normally-off GaN HEMT. The impact of variations in gate length, mole concentration, barrier variations and other important design parameters on the performance of normally-off GaN HEMT is thoroughly investigated. An increase in the gate length causes a decrease in the drain current and transconductance, while an increase in drain current and transconductance can be achieved by increasing the concentration of aluminium (Al). For Al mole fractions of 23%, 25%, and 27%, within Al gallium nitride (AlGaN) barrier, the GaN HEMT devices provide a maximum drain current of 347, 408 and 474 mA/μm and a transconductance of 19, 20.2, 21.5 mS/μm, respectively. Whereas, for Al mole fraction of 10% and 15%, within AlGaN buffer, these devices are observed to provide a drain current of 329 and 283 mA/μm, respectively. Furthermore, for a gate length of 2.4, 3.4, and 4.4 μm, the device is observed to exhibit a maximum drain current of 272, 235, and 221 mA/μm and the transconductance of 16.2, 14, and 12.3 mS/μm, respectively. It is established that a maximum drain current of 997 mA/μm can be achieved with an Al concentration of 23%, and the device exhibits a steady drain current with enhanced transconductance. These observations demonstrate tremendous potential for two-dimensional electron gas (2DEG) for securing of the normally-off mode operation. A suitable setting of gate length and other design parameters is critical in preserving the normally-off mode operation while also enhancing the critical performance parameters at the same time. Due to the normally-on depletion-mode nature of GaN HEMT, it is usually not considered as suitable for high power levels, frequencies, and temperature. In such settings, a negative bias is required to enter the blocking condition; however, in the before-mentioned normally-off devices, the negative bias can be avoided and the channel can be depleted without applying a negative bias.

Single event effect and total dose effect of GaN high electron mobility transistor using heavy ions and gamma rays

The single event effect (SEE) and the total ionizing dose (TID) effect of a commercial enhancement mode gallium nitride (GaN) high electron nobility transistor (HEMT) with p-type gate structure and cascode structure are studied by using the radiation of heavy ions and &lt;sup&gt;60&lt;/sup&gt;Co gamma in this paper. The safe operating areas ofSEE, the sensitive parameters degradation of TID effect and the SEE and TID characteristics of GaN HEMT device are respectively presented. The experimental results show that the SEE and TID effect have less influence on the p-type gate GaN device. The linear energy transfer (LET) threshold of the single event Burnout effect (SEB) is higher than 37 MeV·cm&lt;sup&gt;2&lt;/sup&gt;/mg and the failure threshold of TID effect is above 1M rad (Si) for p-type gate GaN device. However, the GaN HEMT device with cascode structure is much more sensitive to SEE and TID effect than p-type gate GaN device. Under heavy ions at LET of 22 MeV·cm&lt;sup&gt;2&lt;/sup&gt;/mg and a cumulative dose of 200 krad (Si), the SEB phenomenon and parameters-degradation of cascode-type GaN HEMT are respectively observed. Besides, the circuit structure of the cascode-type GaN HEMT device is analyzed by using metallographic microscope imaging and focused ions beam technology. It reveals the possible reason why it is sensitive to SEB and TID for cascode-type GaN HEMT. These results show that the extra carriers caused by heavy ion radiation can tunnel the Schottky barrier formed by gate metal and AlGaN layer, leading to a large source-drain current in GaN HEMT device. Meanwhile, it is shown that the metal oxide semiconductor field-effect transistor in cascode circuit for TP90H180PS GaN HEMT may be the main reason why the cascode-type GaN HEMT is sensitive to TID.

Design and Implementation of a Control Method for GaN-Based Totem-Pole Boost-Type PFC Rectifier in Energy Storage Systems

With the unceasing advancement of wide-bandgap (WBG) semiconductor technology, the minimal reverse-recovery charge Qrr and other more powerful natures of WBG transistors enable totem-pole bridgeless power factor correction to become a dominant solution for energy storage systems (ESS). This paper focuses on the design and implementation of a control structure for a totem-pole boost PFC with newfangled enhancement-mode gallium nitride field-effect transistors (eGaN FETs), not only to simplify the control implementation but also to achieve high power quality and efficiency. The converter is designed to convert a 90–264-VAC input to a 385-VDC output for a 2.6-kW output power. Lastly, to validate the methodology, an experimental prototype is characterized and fabricated. The uttermost efficiency at 230 VAC reaches 99.14%. The lowest total harmonic distortion in the current (ITHD) at high line condition (230 V) attains 1.52% while the power factor gains 0.9985.

The role of SiN/GaN cap interface charge and GaN cap layer to achieve enhancement mode GaN MIS-HEMT operation

The thickness increase of gallium nitride (GaN) cap layer from 2 nm to 35 nm to achieve an enhancement mode GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) with a threshold voltage (Vth) of +0.5 V is studied using TCAD simulations. The simulations are calibrated to measured I-V characteristics of the 1 μm gate length GaN MIS-HEMT with the 2 nm thick GaN cap. A good agreement at low and high drain voltages (VDS=1 V and 5 V) between simulations and measurements is achieved by using a quantum-corrected drift-diffusion transport model. The enhancement mode GaN MIS-HEMT with a GaN cap thickness of 35 nm achieves Vth = + 0.5 V thanks to positive interface traps occurring between the SiN passivation layer and the GaN cap as reported experimentally. The simulations indicate that a parasitic channel is created at the interface between the SiN layer and the 35 nm GaN cap. Our study also shows an increase in the breakdown voltage from 100 V to 870 V when a thickness of the GaN cap layer increases from 15 nm to 35 nm.

Study on Characteristics of Enhancement-Mode Gallium-Nitride High-Electron-Mobility Transistor for the Design of Gate Drivers

An enhancement-mode gallium-nitride high-electron-mobility transistor (E-mode GaN HEMT) operated at high frequency is highly prone to current spikes (di/dt) and voltage spikes (dv/dt) in the parasitic inductor of its circuit, resulting in damage to the power switch. To highlight the phenomena of di/dt and dv/dt, this study connected the drain, source, and gate terminals in series with inductors (LD, LS, and LG, respectively). The objective was to explore the effects of di/dt and dv/dt phenomena and operating frequency (fS) on drain-to-source voltage (Vds), drain-to-source current (Ids), and gate-to-source voltage (Vgs). The experimental method comprised two projects: (1) establishment of a measurement system to assess the change of electrical characteristics of the E-mode GaN HEMT and (2) change of the fS and the inductances (i.e., LD, LS, and LG) in the circuit to measure the changes in Vds, Ids, and Vgs, thus summarizing the experimental results. According to the experimental results on electrical characteristics, a gate driver circuit may be designed to drive and protect the E-mode GaN HEMT while being actually applied to a 120-W synchronous buck converter with an output voltage of 12 V and an output current of 10 A.

Current Trends in the Development of Normally-OFF GaN-on-Si Power Transistors and Power Modules: A Review

Gallium nitride (GaN) power transistors have attracted significant interest in the power electronics industry over the past decade as the next-generation power semiconductor devices. GaN power transistors are suitable for high power and high frequency applications due to their higher electron mobility, temperature tolerance, electrical conductivity, critical breakdown electric field, and breakdown voltage compared to the conventional silicon-based transistors and other wide bandgap (WBG) power transistors. In particular, GaN-on-silicon (GaN-on-Si) technology has opened up the possibility of manufacturing high-performance, low-cost WBG power devices in silicon-compatible fabrication facilities. The first GaN power transistor structure to be developed was the normally-ON depletion mode (D-mode) device. It relies on the highly mobile two-dimension electron gas (2DEG) at the GaN/AlGaN epitaxial layers’ interface to provide very low on-resistance. The normally-OFF enhancement mode (E-mode) GaN power transistor soon became available by controlling the 2DEG using various gate structures. This paper provides a review of the developments of GaN power transistors followed by a survey on current state-of-the-art GaN power technologies and applications, including comparisons between GaN growth substrates and developments of enhancement mode (E-mode) device structures and their process techniques. Moreover, developments of power module designs are also addressed, including gate driver designs and their requirements, and packaging techniques for power transistors and power modules.

A Review of Switching Oscillations of Wide Bandgap Semiconductor Devices

Wide bandgap (WBG) devices offer the advantages of high frequency, high efficiency, and high power density to power converters due to their excellent performance. However, their low parasitic capacitance and fast switching speed also make them more susceptible to switching oscillations. The switching oscillations can cause voltage and current overshoots, shoot-through, electromagnetic interference, additional power loss, and even device damage, which can seriously affect the performance of power converters and systems. However, a comprehensive and in-depth overview is lacking on this topic. This article reviews the types, the causes and negative effects, the effects of parasitic parameters and suppression methods of these switching oscillations, which is helpful for practical engineering. First, the switching oscillations are divided into different types, and their causes and negative effects are reviewed. Then, the effects of different parasitic parameters on the switching oscillations are overviewed. It is found that due to the different physical structures of silicon carbide metal-oxide-semiconductor field-effect transistors, enhancement-mode gallium nitride high-electron mobility transistors (eGaN HEMTs), and cascode GaN HEMTs, the effects are also different. Finally, the main methods of suppressing the switching oscillations are summarized, and the advantages and disadvantages of these methods are presented. Furthermore, future research works on this topic and the conclusion of this paper are drawn, which will help readers deepen their understanding of the switching oscillations of WBG devices, and inspire readers to better use WBG devices for high-frequency and high-efficient power conversion.

Integrated 100 V bootstrap diode with enhanced reverse recovery characteristics for eGaN‐field effect transistor gate drivers

An integrated 100 V bootstrap diode (DBST) with anode engineering based on the double epitaxial process for enhancement mode gallium nitride (eGaN) transistor gate drivers is first proposed in this Letter. On the anode side, the P + dynamic field limiting ring (PDFLR) and the floating metal electrode (FME) are employed. The PDFLR can greatly suppress the peak electric field on both sides of the device during the reverse recovery period, which leads to a significant improvement in reverse recovery robustness. The FME lowers the anode injection efficiency in on-state and increases the hole recombination rate during reverse recovery, therefore, a fast reverse recovery is realised. The partial heavy doped N-type buried layer not only reduces the resistance of the drift region but also shortens the hole extraction path from the drift region to sub-electrode, as a result, reverse recovery tail current can be greatly shortened. Experiments combined with simulations show that the reverse recovery robustness of the optimised proposed DBST is improved by more than 12 times. Furthermore, the reverse recovery charge (Qrr) of the proposed structure is only 3.2 nC, which is 22% lower than that of the conventional device at the same forward current (IF) of 0.1 A.

Temperature‐dependent dynamic R DS,ON under different operating conditions in enhancement‐mode GaN HEMTs

High-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) is a superior candidate to enable higher efficiency and higher power density when compared with silicon power devices in power converter applications. However, the dynamic R DS , ON problem affects the conduction loss of the converter and remains one of the major issues that must be resolved. In this study, a comprehensive experimental evaluation and analysis method of the temperature-dependent dynamic R DS , ON of GaN HEMT in a circuit level is proposed. A commercial E-mode GaN HEMT (GS66508T) is used as a sample to study the temperature-dependent dynamic R DS , ON using a double-pulse-tester. The temperature-dependent dynamic R DS , ON under different DC-link voltages and different load currents are studied and the results show a non-monotonic temperature-dependence of the dynamic R DS , ON . It is concluded that the temperature dependence of the buffer-induced trapping and de-trapping effect, and the temperature dependence of electron mobility together influence the dynamic R DS , ON of E-mode GaN HEMT device during operation. This finding is important since in converter applications the devices are typically operating at elevated temperatures. The proposed comprehensive experimental method can be used to estimate and analyse the dynamic R DS , ON characteristics of other GaN devices.

A Reliable Ultrafast Short-Circuit Protection Method for E-Mode GaN HEMT

A unique three-step short-circuit protection method is proposed for the 650-V enhancement mode (E-mode) gallium nitride high-electron mobility transistor (GaN HEMT). This method can quickly detect the short-circuit event, reduce gate voltage to enhance the device short-circuit capability, and turn off the device under fault after confirmation. Experimental results prove that with this method, the short-circuit fault detection time for E-mode GaN HEMT is shortened from 2 μ s to several tens of nanoseconds, and the device can be successfully protected from fatal failure under high dc bus voltage without mistriggering.

1-kV Input 1-MHz GaN Stacked Bridge $\textit{LLC}$ Converters

In this article, a stacked bridge LLC converter with the split resonant tanks suitable for high input voltage is proposed to reduce the voltage stress of primary-side devices by half. The 650-V enhancement-mode gallium nitride high-electron mobility transistors (eGaN HEMTs) with much lower $R_{ds{\rm{(on)}}}$ and $Q_{g}$ are applied instead of 1700-V silicon carbide (SiC) mosfet s at 1-kV input to produce significantly reduced conduction loss and switching loss at 1 MHz. With eGaN HEMTs switching speed of 2.5 ns at 1-kV input, high dv / dt of 200 kV/ μ s causes large displacement current via the interwinding capacitance of the planar transformers, which distorts the resonant current seriously and causes zero voltage switching (ZVS) lost inducing additional switching loss and root mean square loss. The split resonant tanks solution is proposed to reduce the resonant current distortion to guarantee ZVS and voltage balance over the split capacitance. To reduce the interwinding capacitance, the noninterleaving type windings are proposed to minimize the displacement current from the primary side to secondary side of the matrix transformer. A practical engineering practice of a 1-MHz prototype with 1-kV input and 32-V/3-kW output is built. It achieves the peak efficiency of 96.2% at full load and power density of 107 W/in3, a size reduction of 69% compared to the 300-kHz SiC counterpart.

Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs

The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate. At low voltages (below 100 V), the silicon (Si) MOSFET reigns supreme and at the higher end of the automotive medium-voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the Si insulated-gate bipolar transistor (IGBT). At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs, and enhancement mode GaN high electron mobility transistors (HEMTs). Each technology comes with its unique selling point with gallium nitride (GaN) being well known for ultrahigh speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness, and fast switching while silicon remains clearly dominant in cost and proven reliability. This article comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability, and avalanche ruggedness.

Gate driver IC for enhancement mode GaN power transistors with senseFET reverse conduction detection circuit

Dead-times are necessary in switching output stage to avoid shoot-through current between the high side (HS) and the low side (LS) power transistors. However, excessively long dead-times can lead to unwanted reverse conduction and power loss. Sensing the duration of reverse conductions are especially difficult for high-voltage enhancement mode (e-mode) gallium nitride (GaN) HEMTs due to their fast switching speed. High-precision sensing circuits are required for dead-time correction as the load current changes and to withstand large voltage swings. Traditional CMOS-based sensing circuits (e.g. standard logic gates) are not suitable for GaN-based converters as they can only handle limited voltage ranges. In addition, severe undershoots (up to −4 V) may damage the sensing circuit. Here, a gate driver IC for e-mode GaN power output stages capable of detecting the presence of reverse conduction with a best resolution of 0.66 ns, a dead-time adjustment resolution of 0.33 ns, and with on-chip closed-loop control is presented. In addition, a novel reverse conduction sensing circuit that can accommodate the large voltage swings at the switching node (SW) is also described.

Characterization and Failure Analysis of 650-V Enhancement-Mode GaN HEMT for Cryogenically Cooled Power Electronics

In order to evaluate the feasibility of newly developed gallium nitride (GaN) devices in a cryogenically cooled converter, this article characterizes a 650-V enhancement-mode GaN high-electron mobility transistor (GaN HEMT) at cryogenic temperatures. The characterization includes both static and dynamic behaviors. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature (93 K) is 2.5 times higher than one at room temperature (298 K), and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the ON-resistance of the channel at the cryogenic temperature is only one-fifth of that at room temperature. The corresponding explanations of performance trends at cryogenic temperatures are also given from the view of semiconductor physics. In addition, several device failures were observed during the dynamic characterization of GaN HEMTs at cryogenic temperatures. The ultrafast switching speed-induced high di/dt and dv/dt at cryogenic temperatures amplify the negative effects of parasitics inside the switching loop. Based on failure waveforms, two failure modes were classified, and detailed failure mechanisms caused by ultrafast switching speed are given in this article.