Enhancement-mode Field-effect Transistors Research Articles

Controlling the threshold voltage of a semiconductor field-effect transistor by gating its graphene gate

The threshold voltage of a field-effect transistor (FET) determines its switching and limits the scaling of the supply voltage in the logic gates. Here we demonstrate a GaAs FET with a monolayer graphene gate in which the threshold voltage was externally controlled by an additional control gate. The graphene gate forms a Schottky junction with the transistor channel, modulating the channel conductivity. The control gate sets the work function of the graphene gate, controlling the Schottky barrier height and therefore the threshold voltage, and reduces the subthreshold swing down to ~60 mV dec−1. The change of the threshold voltage was large enough to turn the initially depletion mode FETs into the enhancement mode FETs. This allowed to realize logic gates with a positive switching threshold in which the threshold voltage of each transistor was independently set. The presented FETs can also be operated as dual-gate FETs, which was demonstrated by realizing frequency mixers.

Directly grown Te nanowire electrodes and soft plasma etching for high-performance MoTe2 field-effect transistors

Contact tailoring for two-dimensional (2D) transition metal dichalcogenides (TMDs) to achieve high-performance devices remains a challenge. Fermi-level pinning at 2D TMD–metal contacts leads to a Schottky barrier for contacts. In addition, when there are no dangling bonds between 2D TMDs and contacts, the contact resistance increases. In this study, Te nanowire (NW) contacts were employed for a MoTe2 p-channel of enhancement mode field-effect transistor (FET). The Te NWs were directly grown on 2D MoTe2 film by metal–organic chemical vapor deposition and selectively etched by a soft plasma etching technique for contact isolation. Using t-Te NW contacts on three-atomic-layer MoTe2, a highly effective field-effect mobility of 543.9 cm2/Vs, as well as ohmic contacts and atomic hybridization, was achieved. These results of t-Te NW electrodes provide a novel device structure for p-type 2D TMD transistors with excellent performances. Further, they offer a practical guideline for wafer-scale 2D TMD-based high-performance electronics and optoelectronics.

Why In2O3 Can Make 0.7 nm Atomic Layer Thin Transistors.

In this work, we demonstrate enhancement-mode field-effect transistors by an atomic-layer-deposited (ALD) amorphous In2O3 channel with thickness down to 0.7 nm. Thickness is found to be critical on the materials and electron transport of In2O3. Controllable thickness of In2O3 at atomic scale enables the design of sufficient 2D carrier density in the In2O3 channel integrated with the conventional dielectric. The threshold voltage and channel carrier density are found to be considerably tuned by channel thickness. Such a phenomenon is understood by the trap neutral level (TNL) model, where the Fermi-level tends to align deeply inside the conduction band of In2O3 and can be modulated to the bandgap in atomic layer thin In2O3 due to the quantum confinement effect, which is confirmed by density function theory (DFT) calculation. The demonstration of enhancement-mode amorphous In2O3 transistors suggests In2O3 is a competitive channel material for back-end-of-line (BEOL) compatible transistors and monolithic 3D integration applications.

Improving the signal resolution of semiconductor gas sensors to high-concentration gases

Detecting high-concentration gases is challenging by metal oxide semiconductor (MOX) gas sensors, because the voltage signal would become saturated. In order to solve this problem, the zooming p + n field-effect transistors (FETs) circuit has been designed, combining an n-type enhancement-mode FET (EMFET) and a p-type depletion-mode FET (DMFET). This designed zooming p + n FETs can endow MOX gas sensors with the high signal resolution of ~3.0 V/decade to the 100–2000 ppm (part per million) acetone gas, triple that of MOX gas sensors without FETs (~0.8 V/decade). Meanwhile, this zooming technology is also suitable for detecting other gases at high-concentration, such as 1%–20% LEL (lower explosion limit) methane. The principle of zooming p + n FETs is that with increasing the gas concentration, the suppressing role of the EMFET is firstly induced leading to a reduced signal resolution to the low-concentration target gas; then its suppressing effect becomes saturated and the DMFET starts to switch from ON state to OFF state in the high-concentration target gas, resulting in an amplifying effect herein and thus an enhanced signal resolution. This circuit is promising for the high-concentration gas detection as well as for the multi-functional gas detector design.

Enhancement-mode field-effect transistors based on Ti-doped In2O3 nanowires fabricated by electrospinning

Recently, indium oxide (In2O3) semiconducting nanowires (NWs) have been extensively explored as building blocks for numerous electronic applications. However, most of the field-effect transistors (FETs) based on In2O3 NWs were operated in depletion mode (D-mode), which exhibits negative threshold voltage (VTH) and non-zero current with zero bias. Besides, these devices based on In2O3 NWs still suffer from high leakage current and low on-off current ratios (Ion/off). In this report, high-performance enhancement-mode (E-mode) FETs based on Ti doped In2O3 NWs were successfully integrated. It was found that the device performance could be effectively modulated by adjusting the doping concentration of Ti. The FETs based on In2O3 NWs with Ti doping concentration of 3 mol% exhibited a saturation current of 4.69 × 10−4 A, a subthreshold swing (SS) of 1.54 V/decade, an on/off current ratio of ~1.5 × 108, and a field-effect mobility of 2.53 cm2 V−1 s−1. When high-κ ZrOx dielectrics were successfully integrated into the FETs, the mobility and SS of the designed device were improved to 12.67 cm2 V−1 s−1 and 150 mV/decade, respectively. The inverters based on InTiO NWs/ZrOx FETs were constructed and showed a gain of ~9.5. All of these results demonstrate that Ti-doped In2O3 NWs are promising candidates for large-scale, high-performance and low-power electronic devices.

Chemical vapor deposition of monolayer MoS2 directly on ultrathin Al2O3 for low-power electronics

Monolayer MoS2 has recently been identified as a promising material for high-performance electronics. However, monolayer MoS2 must be integrated with ultrathin high-κ gate dielectrics in order to realize practical low-power devices. In this letter, we report the chemical vapor deposition (CVD) of monolayer MoS2 directly on 20 nm thick Al2O3 grown by atomic layer deposition (ALD). The quality of the resulting MoS2 is characterized by a comprehensive set of microscopic and spectroscopic techniques. Furthermore, a low-temperature (200 °C) Al2O3 ALD process is developed that maintains dielectric integrity following the high-temperature CVD of MoS2 (800 °C). Field-effect transistors (FETs) derived from these MoS2/Al2O3 stacks show minimal hysteresis with a sub-threshold swing as low as ∼220 mV/decade, threshold voltages of ∼2 V, and current ION/IOFF ratio as high as ∼104, where IOFF is defined as the current at zero gate voltage as is customary for determining power consumption in complementary logic circuits. The system presented here concurrently optimizes multiple low-power electronics figures of merit while providing a transfer-free method of integrating monolayer MoS2 with ultrathin high-κ dielectrics, thus enabling a scalable pathway for enhancement-mode FETs for low-power applications.

Bootstrap Voltage and Dead Time Behavior in GaN DC–DC Buck Converter With a Negative Gate Voltage

The low threshold voltage of Gallium Nitride enhancement mode FETs is a concern in synchronous dc–dc buck converters. This paper presents a converter using a gate drive with a negative biased gate voltage on the low-side FET to improve the dV / dt robustness. The resulting much larger voltage drop during the dead time conduction is a concern as it can quickly overcharge the bootstrap capacitor voltage. This paper demonstrates that with a negative biased gate voltage, the rise in the bootstrap capacitor voltage is predominantly caused by the change in effective dead time conduction due to a variation in output load. A spice model to estimate the change is presented and verified. This paper also found that a change in the bootstrap capacitor voltage must be prevented as it leads to a significant change in turn-on dynamics, resulting in higher dV / dt stress with an increase in output load. To prevent a change in bootstrap capacitor voltage, different techniques such as Zener diode clamping and an external free-wheeling Schottky diode are tested and discussed. Finally, a modification of a standard bootstrap circuit using a series inductor is proposed and tested. It has been found to be the most effective method in preventing a variation in the bootstrap capacitor voltage and should be included when using a negative gate drive in a GaN dc–dc buck converter.

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

Undoped and catalyst-free germanium nanowires for high-performance p-type enhancement-mode field-effect transistors

The experimental demonstration of high-performance p-type enhancement-mode field-effect transistors fabricated from undoped and catalyst-free germanium nanowires.

Rational Design of Sub-Parts per Million Specific Gas Sensors Array Based on Metal Nanoparticles Decorated Nanowire Enhancement-Mode Transistors

"One key to one lock" hybrid sensor configuration is rationally designed and demonstrated as a direct effective route for the target-gas-specific, highly sensitive, and promptly responsive chemical gas sensing for room temperature operation in a complex ambient background. The design concept is based on three criteria: (i) quasi-one-dimensional metal oxide nanostructures as the sensing platform which exhibits good electron mobility and chemical and thermal stability; (ii) deep enhancement-mode field-effect transistors (E-mode FETs) with appropriate threshold voltages to suppress the nonspecific sensitivity to all gases (decouple the selectivity and sensitivity away from nanowires); (iii) metal nanoparticle decoration onto the nanostructure surface to introduce the gas specific selectivity and sensitivity to the sensing platform. In this work, using Mg-doped In2O3 nanowire E-mode FET sensor arrays decorated with various discrete metal nanoparticles (i.e., Au, Ag, and Pt) as illustrative prototypes here further confirms the feasibility of this design. Particularly, the Au decorated sensor arrays exhibit more than 3 orders of magnitude response to the exposure of 100 ppm CO among a mixture of gases at room temperature. The corresponding response time and detection limit are as low as ∼4 s and ∼500 ppb, respectively. All of these could have important implications for this "one key to one lock" hybrid sensor configuration which potentially open up a rational avenue to the design of advanced-generation chemical sensors with unprecedented selectivity and sensitivity.

Fractional quantum Hall effect of two-dimensional electrons in high-mobility Si/SiGe field-effect transistors

The fractional quantum Hall (FQH) regime of the Si two-dimensional electron system (2DES) in enhancement-mode field-effect transistors of Si/SiGe heterostructures was probed via electrical transport measurements. At $n\ensuremath{\sim}2.6\ifmmode\times\else\texttimes\fi{}{10}^{11}\phantom{\rule{0.28em}{0ex}}{\text{cm}}^{2}$ with $\ensuremath{\mu}=1.6\ifmmode\times\else\texttimes\fi{}{10}^{6}\phantom{\rule{0.28em}{0ex}}{\text{cm}}^{2}/\text{V}\phantom{\rule{0.16em}{0ex}}\text{s}$, signatures of FQH states at filling factors $\ensuremath{\nu}=4/5$, $6/5$, and $10/7$ were observed, in addition to the FQH states reported in previous studies. The temperature dependence of the FQH states is investigated and comparison is made with previous work done on modulation-doped samples. Results indicate that robustness of the FQH states is dependent on the nature of disorder in the 2DES.

Compressively Strained InxAl1-xN/Al0.22Ga0.78N/GaN (x = 0.245–0.325) Heterostructure Field Effect Transistors with Regrown AlGaN Contact Layers

Compressively strained InxAl1-xN (15 nm)/Al0.22Ga0.78N (3 nm)/GaN heterostructure field effect transistors (FETs) with regrown AlGaN contact layers were fabricated. The increase in compressive strain in InAlN reduced the polarization charge, i.e., the density of two-dimensional electron gas decreased from 6.5 ×1012 to 1.3 ×1012 cm-2 as the In content of InAlN increased from 0.245 to 0.325. With the insertion of the AlGaN layer, electron mobility of as high as 1570 cm2 V-1 s-1 was achieved at the In content of 0.245. Selectively regrown AlGaN contact layers reduced the sheet resistance from 17,000 to 584 Ω/sq. at the access layer for In0.325Al0.675N/Al0.22Ga0.78N/GaN. We fabricated FETs with this structure. The FETs without the regrown AlGaN contact layer did not operate at all owing to the high resistance. In contrast, the devices with the regrown AlGaN did. The maximum transconductance is 60 mS/mm, and the drain current is 0.11 A/mm. The threshold voltage becomes shallower, changing from -3.2 to -0.2 V with the increase in In content from 0.245 to 0.325. These results indicate that it is possible to fabricate enhancement-mode FETs with InAlN/AlGaN/GaN heterostructures.

Field-Effect Transistor Based on Si with LaAlO3−δ as the Source and Drain

N-type LaAlO3−δ thin films are epitaxially grown on p-type Si substrates. An enhancement mode field-effect transistor is constructed with oxygen deficient LaAlO3−δ as the source and drain, p-type Si as the semiconducting channel, and SiO2 as the gate insulator, respectively. The typical current-voltage behavior with field-effect transistor characteristic is observed. The ON/OFF ratio reaches 14 at a gate voltage of 10V, the field-effect mobility is 10 cm 2/V · s at a gate voltage of 2 V, and the transconductance is 5 × 10−6 A/V at a drain-source voltage of 0.8 V at room temperature. The present field-effect transistor device demonstrates the possibility of realizing the integration of multifunctional perovskite oxides and the conventional Si semiconductor.

Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates

We report on InAs enhancement-mode field-effect transistors integrated directly on Si substrates. The transistors consist of vertical InAs nanowires, grown on Si substrates without the use of metal seed particles, and they are processed with a 50-nm-long metal wrap gate and high-kappa gate dielectric. Device characteristics showing enhancement-mode operation are reported. The output characteristics are asymmetric due to the band alignment and band bending at the InAs/Si interface. The implemented transistor geometry can therefore also serve as a test structure for investigating the InAs/Si heterointerface. From temperature-dependent measurements, we deduce an activation energy of about 200 meV for the InAs/Si conduction band offset.

Application of enhancement mode FET technology for wireless subscriber transmit/receive circuits

Single-supply power amplifiers have become the new paradigm in portable phone handsets due to the recent availability of heterojunction bipolar transistor (HBT) and pseudo enhancement mode PHEMT technology. We have developed a true enhancement mode heterostructure insulated-gate FET device (HIGFET) which is suitable for use in both saturated and linear power amplifiers. A three-stage power amplifier designed for 1900-MHz NADC application delivered +30-dBm output power and 41.7% power-added efficiency with an adjacent channel power of -29.8 dBc and alternate adjacent channel power of -48.4 dBc. In addition to this, we have demonstrated excellent noise figure and linearity performance for small-signal applications. At 900 MHz and bias conditions V/sub DS/=1.0 V and I/sub DSQ/=1 mA, a single-stage amplifier achieved a noise figure of 1.17 dB with an associated gain of 18.5 dB. These results make the technology an ideal candidate for application in both transmitter and receiver circuits.

PCFL3: a low-power, high-speed, single-ended logic family

This paper presents a new low-power, high-speed, single-ended logic family called PCFL3. Its operation is based on a bootstrapping technique, used in NMOS. It is fully compatible with direct coupled field-effect transistor logic (DCFL) and two-phase dynamic FET logic (TDFL). PCFL3 is implemented with a standard enhancement/depletion-mode MESFET process and provides all the standard logic functions (NOT, NOR, NAND). Using enhancement-mode FETs only, PCFL3 benefits from good process variation immunity and good noise margins. Measurement results on a ring oscillator are reported. The current consumption of an inverter is reduced by about 53% compared to the DCFL, and the speed is increased by about 50%.

Homoepitaxial Diamond Devices

AbstractDiamond has been proposed as an excellent material for high‐temperature, high‐power, and high‐frequency applications. The interest in diamond electronics is due to its large electric breakdown field, high‐saturated current velocity and high‐thermal conductivity. As silicon and gallium arsenide devices begin to reach their performance limits, there is a need to develop new, better performing materials such as diamond. Significant progress in the development of diamond as a semiconducting material has been made and diamond has been implemented into numerous conventional and novel device designs. In this work homoepitaxial diamond material properties and device performance are reviewed. In summary, the large activation energy of boron‐doped p‐type diamond and phosphorus‐doped n‐type diamond severely limits diamond's use in conventional semiconductor device designs. The large activation energy reduces the number of charge carriers, which limits the current handling capability and produces temperature‐dependent device performance. To overcome diamond's limitations, novel devices, such as enhancement mode field effect transistors (FETs) that use a hydrogenated surface conducting layer or pulsed doped devices with almost complete ionization, have been investigated. These devices require further development. The initial results show promise for high‐temperature, high‐frequency, and high‐power applications.

Design and evaluation of a novel enhancement mode FET logic gate configuration in AlGaAs/GaAs/AlGaAs quantum well HEMT technology

Evaluation of a high-performance logic gate configuration, utilising enhancement mode field effect transistors, is presented in AlGaAs/GaAs/AlGaAs quantum well HEMT technology. The performance of the gate in terms of speed, based on frequency divider measurements, shows a very high-speed operation achieved by utilising the bootstrap effect in the operation of the logic gate. The gate is suitable for the implementation of ultra-high-speed LSI circuits where high speed and noise margin are of critical importance.

Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs

This paper describes an efficient low-power static logic family in GaAs, called PCFL for pseudo-complementary FET logic. Its behavior mimics that of CMOS by compensating the lack of complementary transistors with the use of complementary logic signals. Like any nonratioed logic, PCFL allows the realization of complex gates. It is fully compatible with DCFL and two-phase dynamic FET Logic (TDFL). Using enhancement-mode FET's only, PCFL benefits from good process variations immunity and good noise margins. Measurement results on a ring oscillator, an inverter chain, and a frequency divider are reported. PCFL is shown to operate at 500 MHz with a 0.6 /spl mu/m MESFET process. The power consumption of an inverter is about 10 /spl mu/W at 100 MHz.

A Relationship between Interface Trap Density and Transconductance in 6H-SiC Enhancement Mode Field Effect Transistors

ABSTRACTAn explicit analytical expression relating the interface trap densities and transconductance is derived for enhancement mode field effect transistors without any simplifying assumptions regarding the energy distribution of traps. Using this relationship, the interface trap densities were calculated from transconductance data and compared to experimental data and that provided in the literature. Our expression provides a simple and convenient method to reliably estimate interface traps densities from the readily available transconductance data provided in the pertinent literature.