PCFL3: a low-power, high-speed, single-ended logic family

Abstract

This paper presents a new low-power, high-speed, single-ended logic family called PCFL3. Its operation is based on a bootstrapping technique, used in NMOS. It is fully compatible with direct coupled field-effect transistor logic (DCFL) and two-phase dynamic FET logic (TDFL). PCFL3 is implemented with a standard enhancement/depletion-mode MESFET process and provides all the standard logic functions (NOT, NOR, NAND). Using enhancement-mode FETs only, PCFL3 benefits from good process variation immunity and good noise margins. Measurement results on a ring oscillator are reported. The current consumption of an inverter is reduced by about 53% compared to the DCFL, and the speed is increased by about 50%.