Cache Energy Research Articles

COBRRA: COntention-aware cache Bypass with Request-Response Arbitration

In modern multi-processor systems-on-chip (MPSoCs), requests from different processor cores, accelerators, and their responses from the lower-level memory contend for the shared cache bandwidth, making it a critical performance bottleneck. Prior research on shared cache management has considered requests from cores but has ignored crucial contributions from their responses. Prior cache bypass techniques focused on data reuse and neglected the system-level implications of shared cache contention. We propose COBRRA, a novel shared cache controller policy that mitigates the contention by aggressively bypassing selected responses from the lower-level memory and scheduling the remaining requests and responses to the cache efficiently. COBRRA is able to improve the average performance of a set of 15 SPEC workloads by 49% and 33% compared to the no-bypass baseline and the best-performing state-of-the-art bypass solution, respectively. Furthermore, COBRRA reduces the overall cache energy consumption by 38% and 31% compared to the no-bypass baseline and the most energy-efficient state-of-the-art bypass solution, respectively.

Integration of storage technology oversight: power system and computer engineering analogy

Energy storage, analogous to data storage in a computer system, is one of the enabling technologies that has emerged alongside the widespread use of renewable energy sources in the nation's power grid. This article shows that the underlying platforms for storing data and energy are quite similar. Batteries and hydrogen storage offer significant energy potential, much like a hard disk for storing vast amounts of data in a computer's central processing unit (CPU). A supercapacitor or flywheel storage device can be used to have emergency power on hand, with access times as fast as random access memory (RAM) in modern computers. In this study, we propose an energy-control scheme for caches that is akin to computer engineering and is used to coordinate the operation of multilevel storage systems that incorporate both capacity and access-oriented storage. By supporting the energy-management system, which in turn provides modern plug-and-play functionality, cache energy control helps optimise the system as a whole. Such an integrated system calls for renewable energy generation, local loads, fueling stations, and connections to gas and electric distribution grids. Distribution energy concepts with various storage systems can be easily grasped by drawing parallels between computer engineering and power system integration.

APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime

Due to high static power and low scalability, the traditional SRAM-based cache is not a good solution for image processing applications. Emerging Spin Transfer Torque Magnetic RAM (STT-MRAM) is a promising candidate for cache due to its low leakage power and high density. However, STT-MRAM suffers from high write energy. Therefore, by making use of the ability of tolerating minor errors in image processing applications, this work presents an STT-MRAM based APProximate cache architecture (APPcache+) to write/read approximate data, which can largely reduce the cache energy and improve the STT-MRAM lifetime. APPcache+ includes three main designs. Firstly, we find that there are many similar elements (e.g., pixels in images) in cache lines. Therefore, APPcache+ presents several lightweight similarity-based encoding techniques to remove redundant elements, thus shortening the data size and reducing the energy of STT-MRAM cache. Secondly, we design a partial read scheme to reduce the read energy of the STT-MRAM cache. In the traditional decompression process, the whole line is fetched into the decompressor, leading to unnecessary read energy. The partial read scheme can largely reduce read energy while keeping the overhead low. Thirdly, we observe the encoding schemes may lead to bit write imbalance. Therefore, we propose a lightweight Ping-Pong intra-line wear-leveling scheme to improve the lifetime. Compared with the baseline, extensive evaluation results show that our APPcache+ can largely reduce the overall energy by 32.58%, improve lifetime by 40.7% with only 2.2% performance degradation and 1.86% output quality loss.

Energy-efficient proactive caching with multipath routing

The ever-continuing explosive growth of on-demand content distribution has imposed great pressure on mobile/wireless network infrastructures. To ease congestion in the network and to increase perceived user experience, caching of popular content closer to the end-users can play a significant role and as such this issue has received significant attention over the last few years. Additionally, energy saving is treated as a fundamental requirement in the design of next-generation mobile networks. However, there has been little attention to the overlapping area between energy saving and network caching especially when considering multipath routing. To this end, this paper proposes an energy-efficient caching with multipath routing support. The proposed scheme provides a joint anchoring of popular content into a set of potential caching nodes with optimized multipath support whilst ensuring a balance between transmission and caching energy cost. The proposed model also considers different content delivery modes, such as multicast and unicast . Two separated Integer-Linear Programming (ILP) models are formulated for each delivery mode. To tackle the curse of dimensionality we then provide a greedy simulated annealing algorithm , which not only reduces the time complexity but also provides a competitive performance. A wide set of numerical investigations reveal that the proposed scheme reduces the energy consumption up to 75% compared with other widely used caching approaches under the premise of network resource limitation. Sensitivity analysis to different parameters is also meticulously discussed in this paper.

Deep Reinforcement Learning-Based Energy-Efficient Edge Computing for Internet of Vehicles

Mobile network operators (MNOs) allocate computing and caching resources for mobile users by deploying a central control system. Existing studies mainly use programming and heuristic methods to solve the resource allocation problem, which ignores the energy cost problem that is really significant to the MNO. To solve this problem, in this article, we design a joint computing and caching framework by integrating deep deterministic policy gradient (DDPG) algorithm. Especially, we focus on the Internet of Vehicles scenario, which needs the support of mobile network provided by MNO. We first formulate an optimization problem to minimize MNO’s energy cost by considering the computation and caching energy costs jointly. Then, we turn the formulated problem into a reinforcement learning problem and utilize DDPG methods to solve this problem. The final simulation result shows that our solution can reduce energy costs by more than 15%, while ensuring the tasks can be completed on time.

Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads

Wearable devices have grown exponentially in popularity in both consumer and industrial applications in recent years. Despite their stringent area and energy constraints, these devices are processing increasingly complex and data-rich workloads, necessitating innovative area- and energy-efficient computing solutions and architectures. This paper explores spin-transfer torque RAM (STT-RAM) as a candidate for designing area- and energy-efficient wearable processor caches. First, we analyze the memory footprints of 16 real-world wearable workloads and compare them to general-purpose benchmarks like SPEC 2017 and MiBench. Then, we analyze the wearable workloads’ memory characteristics to reveal that wearable workloads are highly read-intensive, making them less vulnerable than general-purpose workloads to the write latency/energy overheads inherent in STT-RAM caches. Our analysis also reveals that wearable workloads have low cache variability needs, and their cache blocks exhibit short and stable lifetimes. Against the background of this analysis, we explore the tradeoffs of STT-RAM cache architecture designs for the wearable workloads. Specifically, we explore a simple adaptable design that aims to optimize latency or energy, based on runtime needs, without introducing significant design or area overhead. Our analysis shows that STT-RAM caches offer much promise for energy- and area-efficient wearable computing, without introducing much performance overheads.

An Energy Reward-Based Caching Mechanism for Information-Centric Internet of Things.

Existing information-centric networking (ICN) designs for Internet of Things (IoT) mostly make caching decisions based on probability or content popularity. From the energy-efficient perspective, those strategies may not always be energy efficient in resource-constrained IoT because without considering the energy reward of caching decisions, inappropriate routers and content objects may be selected for caching, which may lead to negative energy rewards. In this paper, we analyze the energy consumption of content caching and content retrieval in resource-constrained IoT and calculate caching energy reward as a key metric to measure the energy efficiency of a caching decision. We then propose an efficient cache placement and cache replacement mechanism based on the caching energy reward to improve the energy efficiency of caching decisions. Through analysis and experimental results, we show that the proposed mechanism achieves a significant improvement in terms of energy efficiency, stretch ratio, and cache hit ratio compared to state-of-the-art caching schemes.

An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance

Conventional 2-level cache architecture is not efficient in mobile systems when small programs that do not require the large L2 cache run. Bypassing the L2 cache for those small programs has two benefits. When only a single program runs, bypassing the L2 cache allows to power it down removing its leakage energy consumption. When multiple programs run simultaneously on multiple cores, small programs bypass the L2 cache while large programs use it. This decreases conflicts in the L2 cache among those programs increasing overall performance. From our experiments using cycle-accurate performance and energy simulators, our proposed L2 cache architecture supporting bypassing is shown to be effective in reducing L2 cache energy consumption and increasing overall performance of programs.

Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality Similarity

This article presents a novel energy-efficient cache design for massively parallel, throughput-oriented architectures like GPUs. Unlike L1 data cache on modern GPUs, L2 cache shared by all of the streaming multiprocessors is not the primary performance bottleneck, but it does consume a large amount of chip energy. We observe that L2 cache is significantly underutilized by spending 95.6% of the time storing useless data. If such “dead time” on L2 is identified and reduced, L2’s energy efficiency can be drastically improved. Fortunately, we discover that the SIMT programming model of GPUs provides a unique feature among threads: instruction-level data locality similarity, which can be used to accurately predict the data re-reference counts at L2 cache block level. We propose a simple design that leverages this Lo cality S imilarity to build an energy-efficient GPU L2 Cache , named LoSCache . Specifically, LoSCache uses the data locality information from a small group of cooperative thread arrays to dynamically predict the L2-level data re-reference counts of the remaining cooperative thread arrays. After that, specific L2 cache lines can be powered off if they are predicted to be “dead” after certain accesses. Experimental results on a wide range of applications demonstrate that our proposed design can significantly reduce the L2 cache energy by an average of 64% with only 0.5% performance loss. In addition, LoSCache is cost effective, independent of the scheduling policies, and compatible with the state-of-the-art L1 cache designs for additional energy savings.

CONDENSE: A Moving Target Defense Approach for Mitigating Cache Side-Channel Attacks

Common consumer electronic devices (including smartphones, smart TVs, personal computers, etc.) feature increasingly complex processors for the required computations. These processors typically feature caches, which substantially improve the devices’ performance, but may also be prone to side-channel attacks, wherein an attacker measures and analyzes the side-channel data in order to deduce private information. In this article, we explore CONDENSE: Configurability-Driven Security as a viable low-overhead technique for mitigating security vulnerabilities in caches. CONDENSE takes advantage of runtime reconfigurable caches to provide a moving target defense against side-channel attacks, while also optimizing the cache's energy consumption. Experimental results reveal that employing cache configurability as a defense mechanism is promising and warrants further studies.

Energy-aware caching and collaboration for green communication systems

Social networks and mobile applications tend to enhance the need for high-quality content access. To meet the growing demand for data services in 5G cellular networks, it is important to develop effective content caching and distribution techniques, to reduce redundant data transmission and thereby improve network efficiency significantly. It is anticipated that energy harvesting and self-powered Small Base Stations' (SBS) are the rudimentary constituents of next-generation cellular networks. However, uncertainties in harvested energy are the primary reasons to opt for energy-efficient (EE) power control schemes to reduce SBS energy consumption and ensure the quality of services for users. Using edge collaborative caching, such EE design can also be achievable via the use of the content cache, decreasing the usage of capacity limited SBSs backhaul and reducing energy utilisation. Renewable energy (RE) harvesting technologies can be leveraged to manage the huge power demands of cellular networks. To reduce carbon footprint and improve energy efficiency, we tailored a more practical approach and propose green caching mechanisms for content distribution that utilise the content caching and renewable energy concept. Simulation results and analysis provide key insights that the proposed caching scheme brings a substantial improvement regarding content availability, cache storage capacity at the edge of cellular networks, enhances energy efficiency, and increases cache collaboration time up to 24%. Furthermore, self-powered base stations and energy harvesting are an ultimate part of next-generation wireless networks, particularly in terms of optimum economic sustainability and green energy in developing countries for the evolution of mobile networks.

Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags

The cache system dissipates a significant amount of energy compared to the other memory components. This will be intensified if a cache is designed with a set-associative structure to improve the system performance because the parallel accesses to the entries of a set for tag comparisons lead to even more energy consumption. In this paper, a novel method is proposed as a combination of a counting Bloom filter and partial tags to mitigate the energy consumption of set-associative caches. This new hybrid method noticeably decreases the cache energy consumption especially in highly-associative instruction caches. In fact, it uses an enhanced counting Bloom filter to predict cache misses with a high accuracy as well as partial tags to decrease the overall cache size. This way, unnecessary tag comparisons can be prevented and therefore, the cache energy consumption is considerably reduced. Based on the simulation results, the proposed method provides the energy reduction from 22% to 31% for 4-way–32-way set-associative L1 caches bigger than 16[Formula: see text]kB running the MiBench programs. The improvements are attained with a negligible system performance degradation compared to the traditional cache system.

AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To this end, instead of protecting all cache lines using strong ECCs, AWARE employs a simple ECC that guarantees a given reliability level for the majority of writes. Meanwhile, when a data block with high error rate is written, one way in the target set is adaptively configured to store the check bits of a strong ECC for this block. The evaluation results show that, compared with conventional ECCs, AWARE reduces the ECC area by about 81.2 percent and the cache energy consumption by about 9.5 percent. These reductions are achieved by imposing less than 1 percent performance overhead and without compromising the reliability.

Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems

Cache vulnerability due to soft errors is one of the reliability concerns in embedded systems. Dynamic reconfiguration techniques are widely studied for improving cache energy without considering the implications of cache vulnerability. Maintaining a useful data longer in the cache can be beneficial for energy improvement due to reduction in miss rates, however, longer data retention negatively impacts the vulnerability due to soft errors. This paper studies the tradeoff between energy efficiency improvement and reduction in cache vulnerability during cache reconfiguration. We propose a heuristic approach for both intertask and intratask cache reconfiguration in multitasking systems. Experimental results demonstrate that our proposed approach can significantly improve both vulnerability (25% on average) and energy efficiency (21% on average) for data cache without violating real-time constraints.

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

Much research has shown that applications have variable runtime cache requirements. In the context of the increasingly popular Spin-Transfer Torque RAM (STT-RAM) cache, the retention time, which defines how long the cache can retain a cache block in the absence of power, is one of the most important cache requirements that may vary for different applications. In this paper, we propose a Logically Adaptable Retention Time STT-RAM (LARS) cache that allows the retention time to be dynamically adapted to applications' runtime requirements. LARS cache comprises of multiple STT-RAM units with different retention times, with only one unit being used at a given time. LARS dynamically determines which STT-RAM unit to use during runtime, based on executing applications' needs. As an integral part of LARS, we also explore different algorithms to dynamically determine the best retention time based on different cache design tradeoffs. Our experiments show that by adapting the retention time to different applications' requirements, LARS cache can reduce the average cache energy by 25.31%, compared to prior work, with minimal overheads.

Decoupled Fused Cache

DRAM caches have shown excellent potential in capturing the spatial and temporal data locality of applications capitalizing on advances of 3D-stacking technology; however, they are still far from their ideal performance. Besides the unavoidable DRAM access to fetch the requested data, tag access is in the critical path, adding significant latency and energy costs. Existing approaches are not able to remove these overheads and in some cases limit DRAM cache design options. For instance, caching DRAM cache tags adds constant latency to every access; accessing the DRAM cache using the TLB calls for OS support and DRAM cachelines as large as a page; reusing the last-level cache (LLC) tags to access the DRAM cache limits LLC performance as it requires indexing the LLC using higher-order address bits. In this article, we introduce Decoupled Fused Cache , a DRAM cache design that alleviates the cost of tag accesses by fusing DRAM cache tags with the tags of the on-chip LLC without affecting LLC performance. In essence, the Decoupled Fused Cache relies in most cases on the LLC tag access to retrieve the required information for accessing the DRAM cache while avoiding additional overheads. Compared to current DRAM cache designs of the same cacheline size, Decoupled Fused Cache improves system performance by 6% on average and by 16% to 18% for large cacheline sizes. Finally, Decoupled Fused Cache reduces DRAM cache traffic by 18% and DRAM cache energy consumption by 7%.

<italic>PhLock:</italic> A Cache Energy Saving Technique Using Phase-Based Cache Locking

Caches are commonly used to bridge the processor-memory performance gap in embedded systems. Since embedded systems typically have stringent design constraints imposed by physical size, battery capacity, and real-time deadlines much research focuses on cache optimizations, such as improved performance and/or reduced energy consumption. Cache locking is a popular cache optimization that loads and retains/locks selected memory contents from an executing application into the cache to increase the cache’s predictability. Previous work has shown that cache locking also has the potential to improve cache energy consumption. In this paper, we introduce phase-based cache locking, PhLock , which leverages an application’s varying runtime characteristics to dynamically select the locked memory contents to optimize cache energy consumption. Using a variety of applications from the SPEC2006 and MiBench benchmark suites, experimental results show that PhLock is promising for reducing both the instruction and data caches’ energy consumption. As compared to a nonlocking cache, PhLock reduced the instruction and data cache energy consumption by an average of 5% and 39%, respectively, for SPEC2006 applications, and by 75% and 14%, respectively, for MiBench benchmarks.

L2 cache performance analysis for MPSoC by tag – comparision

Memory systems in many applications are becoming increasingly large, contributing to many challenges in the memory management that has led to many method to manage memory. The tag comparison consumes large amount of cache energy. Current methods provide tag comparison cache or failure of the expected cache. Here is proposed an idea based on new call Comparing Tag stages, filter bloom is presented to improve the efficiency of the cache to predict failure and partial tag comparison for the cold line of verification and full comparison check for direct labels. Moreover, the administration of the cache that is filled with cache lines occurs when there is a cache miss. Today's embedded applications use MPSoC. The MPSoC consists of the following ie more than one processors, shared memory among the processors available and a global off-chip memory. Planning of the activities of an integrated application processor and memory partition between processors are two main critical problem. Here, for an integrated application, both task scheduling and partitioning the integrated available L2 cache to reduce the runtime approach is used.

Trade-off in optimizing energy consumption and end user quality of experience in radio access network

To reduce network access latency, network traffic volume and server load, caching capacity has been proposed as a component of evolved Node B (eNodeB) in the ratio access network (RAN). These eNodeB caches reduce transport energy consumption but lead to additional energy cost by equipping every eNodeB with caching capacity. Existing researches focus on how to minimize total energy consumption, but often ignore the trade-off between energy efficiency and end user quality of experience, which may lead to undesired network performance degradation. In this paper, for the first time, we build an energy model to formulate the problem of minimizing total energy consumption at eNodeB caches by taking a trade-off between energy efficiency and end user quality of experience. Through coordinating all the eNodeB caches in the same RAN, the proposed model can take a good balance between caching energy and transport energy consumption while also guarantee end user quality of experience. The experimental results demonstrate the effectiveness of the proposed model. Compared with the existing works, our proposal significantly reduces the energy consumption by approximately 17% while keeps superior end user quality of experience performance.

Data-type specific cache compression in GPGPUs

In this paper, we evaluate compressibility of L1 data caches and L2 cache in general-purpose graphics processing units (GPGPUs). Our proposed scheme is geared toward improving performance and power of GPGPUs through cache compression. GPGPUs are throughput-oriented devices which execute thousands of threads simultaneously. To handle working set of this massive number of threads, modern GPGPUs exploit several levels of caches. GPGPU design trend shows that the size of caches continues to grow to support even more thread level parallelism. We propose using cache compression to increase effective cache capacity, improve performance, and reduce power consumption in GPGPUs. Our work is motivated by the observation that the values within a cache block are similar, i.e., the arithmetic difference of two successive values within a cache block is small. To reduce data redundancy in L1 data caches and L2 cache, we use low-cost and implementation-efficient base-delta-immediate (BDI) algorithm. BDI replaces a cache block with a base and an array of deltas where the combined size of the base and deltas is less than the original cache block. We also study locality of fields in integer and floating-point numbers. We found that entropy of fields varies across different data types. Based on entropy, we offer different BDI compression schemes for integer and floating-point numbers. We augment a simple, yet effective, predictor that determines type of values dynamically in hardware and without the help of a compiler or a programmer. Evaluation results show that on average, cache compression improves performance by 8% and saves energy of caches by 9%.