Energy-efficient Switching Scheme Research Articles

An energy-efficient 16 MS/s 10-bit SAR ADC with MSB-block switching scheme

An energy-efficient MSB-block switching scheme without common-mode voltage variation for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. Benefit from a pair of extra switches embedded in the capacitive digital-to-analog converter (CDAC), the proposed MSB-block switching scheme can reduce switching energy without further reducing the capacitor unit. The proposed switching scheme can achieve 93.8 % and 49.9 % savings in switching energy compared with the conventional switching scheme and the Vcm-based switching scheme, and the simulated differential-nonlinearity (DNL) and integrated-nonlinearity (INL) are 0.160 and 0.156LSB, respectively. The proposed switching scheme is verified in a 1.2-V 10-bit 16 MS/s SAR ADC in 65 nm CMOS technology. At maximum sampling rate, the proposed SAR ADC achieves an effective number of bits (ENOB) of 9.50 and a power consumption of 103.5μW, leading to a Figure of Merit of 8.93 fJ/Conversion-step.

A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converter with One Least Significant Bit Common-Mode Voltage Variation.

A 9-10-bit adjustable and energy-efficient switching scheme for SAR ADC with one-LSB common-mode voltage variation is proposed. Based on capacitor-splitting technology and common-mode conversion techniques, the proposed switching scheme reduces the DAC switching energy by 96.41% compared to the conventional scheme. The low complexity and the one-LSB common-mode voltage offset of this scheme benefit from the simultaneous switching of the reference voltages of the capacitors corresponding to the positive array and the negative array throughout the entire reference voltage switching process, and the reference voltage of each capacitor in the scheme does not change more than two voltages. The post-layout result shows that the ADC achieves the 54.96 dB SNDR, the 61.73 dB SFDR, and the 0.67 μw power consumption with the 10-bit mode and the 48.33 dB SNDR, the 54.17 dB SFDR, and the 0.47 μw power consumption with the 9-bit mode in a 180 nm process with a 100 kS/s sampling frequency.

A Wireless Multimodal Physiological Monitoring ASIC for Animal Health Monitoring Injectable Devices.

Utilizing injectable devices for monitoring animal health offers several advantages over traditional wearable devices, including improved signal-to-noise ratio (SNR) and enhanced immunity to motion artifacts. We present a wireless application-specific integrated circuit (ASIC) for injectable devices. The ASIC has multiple physiological sensing modalities including body temperature monitoring, electrocardiography (ECG), and photoplethysmography (PPG). The ASIC fabricated using the CMOS 180 nm process is sized to fit into an injectable microchip implant. The ASIC features a low-power design, drawing an average DC power of 155.3 µW, enabling the ASIC to be wirelessly powered through an inductive link. To capture the ECG signal, we designed the ECG analog frontend (AFE) with 0.3 Hz low cut-off frequency and 45-79 dB adjustable midband gain. To measure PPG, we employ an energy-efficient and safe switched-capacitor-based (SC) light emitting diode (LED) driver to illuminate an LED with milliampere-level current pulses. A SC integrator-based AFE converts the current of photodiode with a programmable transimpedance gain. A resistor-based Wheatstone Bridge (WhB) temperature sensor followed by an instrumentation amplifier (IA) provides 27-47 °C sensing range with 0.02 °C inaccuracy. Recorded physiological signals are sequentially sampled and quantized by a 10-bit analog-to-digital converter (ADC) with the successive approximation register (SAR) architecture. The SAR ADC features an energy-efficient switching scheme and achieves a 57.5 dB signal-to-noise-and-distortion ratio (SNDR) within 1 kHz bandwidth. Then, a back data telemetry transmits the baseband data via a backscatter scheme with intermediate-frequency assistance. The ASIC's overall functionality and performance has been evaluated through an invivo experiment.

A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications.

A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of Vcm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low sampling error sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrate that the ADC achieves a 61.77 dB SNDR and a 78.06 dB SFDR and consumes 4.45 μW of power in a 180 nm process with a 1 V power supply, a full-swing input signal frequency of 93.33 kHz, and a sampling rate of 200 kS/s.

A Bridged-Switch Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converters with a Low-Complexity Capacitor Drive Circuit

In recent years, due to the rise of the Internet of Things (IoT), various sensors have come to be in great demand for IoT devices. Analog-to-digital converters (ADCs) act as an important part of receivers in sensors. To improve the uptime of IoT devices, a bridged-switch energy-efficient switching scheme for successive approximation register (SAR) ADCs with a low-complexity capacitor drive circuit is proposed. The technique of top-plate sampling and closed-loop charge recycling is used in the proposed switching scheme so that neither the first nor the second comparison consumes switching energy. The third comparison uses bridge switches to connect the subarray to the main array, effectively reducing switching’s energy consumption. Only the least significant bit (LSB) is dependent on the accuracy of Vcm; thus, the last comparison consumes little switching energy. The proposed switching scheme achieves an average switching energy value of 47.5 CV2ref, which is 96.52% lower than that of the conventional capacitor switching scheme and reduces the area by 75%. The other major circuit modules employed are bootstrapped switches, a fully dynamic comparator, and dynamic SAR logic. The proposed ADC was simulated under the conditions of 180 nm CMOS process and 1 MS/s, resulting in a 9.8-bit effective number of bits (ENOB), a signal-to-noise and distortion ratio (SNDR) of 60.76 dB, a spurious-free dynamic range (SFDR) of 69.85 dB, a power consumption of 14.7 μW, and a figure of merit (FoM) of 16.55 fJ/conv.-step.

Analysis and design of a new shift monotonic switching procedure for SAR ADC

A New Shift Monotonic Switching (NSMS) DAC capacitor array switching scheme suitable for successive approximation register Analog-to-Digital Converters (SAR ADCs) is proposed. The proposed DAC switching scheme utilizes two DAC arrays to achieve double-swing input signals without increasing the size of the capacitor array. In this paper, a 10-bit SAR ADC behavioral-level model is established through detailed analysis of the previously proposed energy-efficient DAC capacitor array switching scheme and the proposed NSMS switching scheme. Compared to the merged capacitor switching (MCS) scheme, the proposed NSMS switching scheme achieves an average switching energy optimization of 88% while maintaining better linearity. Additionally, for low-sampling-frequency applications, an improved SAR ADC architecture based on the NSMS capacitor array switching scheme is provided, which further reduces power consumption and system overhead.

A 99.93% energy-efficient switching scheme for SAR ADC without switching energy in the first three MSBs

This paper presents a highly energy-efficient and area-saving switching scheme for successive approximation register (SAR) analog-to-digital converters. By switching the voltages of all the bottom plates of capacitors in one side simultaneously by the same voltage level, the proposed switching scheme consumes no switching energy in the first three comparison cycles during which most of the switching energy is consumed. This switching method achieves a 99.93% reduction in switching energy and 97.6% less number of total capacitors over the conventional SAR switching scheme. In addition, the root mean square (RMS) of the maximum differential nonlinearity (DNL) and the maximum integral nonlinearity (INL) are 0.318 LSB and 0.32 LSB, respectively.

A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor

A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor is presented. Based on the two sub-capacitor arrays architecture and the common-mode technique, the proposed switching scheme achieves 98.45% less switching energy over the conventional architecture with common-mode shift in one LSB. The comparator uses a low power dynamic comparator. The sampling switch adopts a bootstrap circuit with low sampling error. SAR logic is composed of Bit-Slice circuit with low power consumption and few transistors. Simulated in 180 nm CMOS process and 1 MS/s sampling rate, the ADC achieves the 60.06 dB SNDR, the 75.43 dB SFDR and the 10.45 μW power consumption.

A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications.

This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator and automatic ON/OFF SAR logic for biomedical applications. The energy-efficient switching scheme achieves an average digital-to-analog converter switching energy of 63.56 CVref2, achieving a reduction of 95.34% compared with the conventional capacitor switching scheme for CDACs. With the switching scheme, the ADC can lower the dependency on the accuracy of Vcm and complexity of DAC control logic and DAC driver circuit. Moreover, dynamic circuits and automatic ON/OFF technology are used to reduce power consumption of comparator and SAR logic. The prototype is designed and fabricated in a 180 nm CMOS with a core size of 500 μm × 300 μm (0.15 mm2). It consumes 7.6 nW at 1 kS/s sampling rate and 1.8-V supply with an achieved signal-to-noise-and distortion ratio of 45.90 dB and a resulting figure of merit of 51.7 fJ/conv.-step.

An energy-efficient switching scheme based on a splitting structure

An energy-efficient switching scheme is proposed for successive approximation register analog-to-digital converters (SAR ADCs). Benefiting from the method based on MSB splitting and LSB splitting capacitor arrays, the total capacitance of DAC is reduced by 87%. Based on the switching method of the proposed scheme, the CDACs feed energy back to the reference power supply during the switching process to reduce energy consumption. And the proposed scheme achieves 99.61% energy saving reduction over the conventional scheme. In addition, adopting the strategy of unilateral switching can greatly reduce the energy consumption of switching driving, and at the same time reduce the complexity of the control logic. Using the LSB splitting capacitive technique, C-2C scheme is adopted without reducing the unit capacitance, which effectively improves the error caused by capacitance mismatch. The strategy of group reset is adopted, and there is no energy consumption during the reset process. The simulation results show that the differential nonlinearity and integral nonlinearity are 0.335LSB and 0.397LSB, respectively.

Low-Power Switching Scheme with Quarter Reference Voltage Sources for SAR ADCs

In this paper, an energy-efficient switching scheme with additional quarter-reference voltage sources in a successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for a low power and small area device for frequency modulated continuous wave (FMCW) radar transceivers. Recently, state-of-the-art ADCs have adopted a configuration that also uses Vref/2 as the reference voltage of the ADCs to improve the switching energy of capacitive digital-to-analog converter (CDAC). The proposed switching configuration additionally uses Vref/4 and 3Vref/4 reference voltages as the reference voltage of CDAC. Compared to state-of-the-art configurations that use the additional reference voltage of Vref/2, the average switching energy, and the total capacitance of CDAC in the proposed configuration are reduced by about 87.5% and 50%, respectively. In this switching scheme, the CDAC output voltage gradually converges to Vref/2, like with conventional SAR ADCs, which minimizes the dynamic offset that deteriorates the linearity of the SAR ADC.

An energy-efficient switching scheme based on the improved semi-resting DAC structure and floating-capacitor technique for SAR ADC

An energy-efficient switching scheme based on the improved semi-resting DAC structure and floating-capacitor technique for SAR ADC

High energy-efficient switching scheme for SAR ADC with low common-mode level variation

This letter presents a novel high energy-efficient switching scheme with low common-mode level variation for successive approximation register (SAR) analog-to-digital converters. Benefit from the merge capacitor split and C-2C techniques, the proposed switching scheme achieves 98% saving in switching energy and 86.91% reduction in capacitor area over the conventional scheme without reset energy. Compared with state-of-the-art works, the area saving is the highest. Meanwhile, the common-mode level at the comparator input is Vcm except the second cycle and the last cycle during SAR ADC conversion phase, which reduces the dynamic offset of the comparator greatly.

A high energy-efficiency and low-area switching scheme for SAR ADCs

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC switches is lower than the conventional and some other methods, which avoids further complicating the logic circuit as well as increasing wiring and area. Moreover, only one voltage source is used as a reference voltage, which makes us needless to have an extra voltage source that must be very accurate.

An energy-efficient switching scheme with low common-mode voltage variation and no-capacitor-splitting DAC for SAR ADC

An energy-efficient switching scheme with low common-mode voltage variation and simple capacitor array for successive approximation register (SAR) analog-to-digital converters (ADCs) is presented. The proposed scheme adopts simple binary weighted capacitor array without capacitor-splitting, and consumes no switching energy in the first two comparison cycles. The behavioural simulation shows the proposed scheme achieves 98.45% saving in switching energy and 75% saving in total capacitors area compared with the conventional switching scheme. Furthermore, the voltage variation on positive and negative sides of capacitive digital-to-analog converter (CDAC) is equal in magnitude and opposite in direction until the last bit cycle, therefore the dynamic common-mode voltage variation range of CDAC is only 0.5LSB. Employing the proposed switching scheme, a 10-bit 200-kS/s 0.6-V SAR ADC is designed in 40-nm CMOS technology. Post-layout simulation results indicate that a SNDR of 57.1 dB can be achieved with the Nyquist input at 200-kS/s. The figure-of-merit of the proposed ADC is 1.37fJ/conversion-step.

A Four-Level Switching Scheme for SAR ADCs with 87.5% Area Saving and 97.85% Energy-Reduction

In this paper, a new highly energy-efficient switching scheme is presented for successive approximation register analogue-to-digital converters. The proposed method applies a four-level switching strategy to reduce the switching energy to one of the lowest levels reported yet. Also, the controller of this method has low complexity compared to the other procedures. In contrast to the conventional scheme, the switching energy is reduced by 97.85% and the total capacitor size is decreased by 87.5%. Moreover, under the condition of the 50-times Monte-Carlo simulation for capacitor mismatch and reference voltages mismatch (Vref/2 and Vref/4), the mean value of the effective number of bit (ENOB) with standard deviation of 1% is 7.4 and 7.33 bits, respectively, while the ENOB value without any mismatches is 7.51 bits with sampling frequency of 1MS/s. It is noteworthy that the Monte-Carlo simulations are performed in Spectre simulator in Cadence with consideration all of non-idealities such as transistor charge injection, clock jitter and clock feedthrough. In other words, accurate and electrical simulation is performed instead of behavioral simulation. As a result, the bar graph of the ENOB values is plotted in MATLAB. In addition, the maximum and minimum of DNL/INL values are between − 0.3/0.3 LSB.

Low-power asymmetric switching scheme with segmented capacitive architecture for SAR ADCs

In this paper, an energy-efficient asymmetric switching scheme with segmented capacitive architecture in successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed for biomedical applications. Based on the segmented digital-to-analog converter architecture, the proposed method curtails the area overhead by 92% in comparison with the conventional switching method. Additionally, combining a new tri-level switching scheme, the one-side technique and the split-MSB mode, the proposed asymmetric switching scheme achieves 99.68% less switching energy over the conventional SAR ADC.

Energy-efficient DAC switching scheme with operation-mode configurability for SAR ADCs

An energy-efficient digital-to-analogue converter switching scheme with operation-mode configurability is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). The operation-mode configurability of the SAR ADC is realized by utilizing the single-side switching method, which can achieve operation-mode change between differential mode and single-ended mode. Compared to conventional scheme, the proposed switching scheme improves the energy-efficiency by 99.23% and 96.9% for differential mode and single-ended mode, respectively.

A 92.1% area-efficient charge sharing switching scheme with near zero reset energy for SAR ADCs

This paper presented a highly energy-efficient and area-efficient capacitor switching scheme with near zero reset energy for successive approximation register analog-to-digital converters. A hybrid switching scheme and a single-side dummy capacitor charge sharing method are proposed for the determination of multiple high bits and the low three bits, respectively. Based on the asymmetric capacitance array, the proposed switching scheme achieves 99.24% savings in switching energy and 92.1% reduction in total capacitance in comparison with the conventional switching method.

A 10-Bit 120 kS/s SAR ADC Without Reset Energy for Biomedical Electronics

A 10-bit 120 kS/s successive-approximation-register analog-to-digital converter (SAR ADC) is realized for implantable multichannel neural recording system. In order to reduce power consumption and area occupation, an improved energy-efficient VCM-based switching scheme is proposed. Different from the monotonic switching scheme, the switching procedure for each bit cycle of this proposed scheme is almost symmetrical, which facilitates the comparator design. Additionally, since all these capacitors are connected to VCM in the sampling phase, the reset energy of this switching scheme is zero. Bootstrapped sampling switches are employed for linearity improvement. Realized in 0.18-µm CMOS, the proposed ADC occupies an active area of 0.13 mm2. Including the I/O and two 4-to-1 multiplexers, the power consumption is 2.97 µW at 120 kS/s sampling rate. The figure-of-merit of this proposed SAR ADC is about 36.9 fJ/conversion-step.