Energy-efficient Switching Scheme Research Articles

Energy-efficient and two-step structure switching scheme based on reference-free for SAR ADC

A novel capacitor switching scheme for successive approximation register analogue-to-digital converters is proposed which can achieve a high energy saving, with only two references, Vref and gnd. Due to the two-step architecture is adopted here, the total capacitance is reduced by 48.44% over the conventional structure. Furthermore, based on the most-significant bit capacitor using split-capacitor procedure and monotonic switching method, the proposed switching scheme achieves 99.74% less switching energy over the conventional architecture. Note that during the design procedure, the complexity of logic and auxiliary power supply circuits are further reduced by the lack of the common voltage (Vcm). Besides the significant energy saving in the switching process, the proposed capacitor architecture also has zero consumption in reset energy. Matlab simulation results show the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.644 LSB and 0.825 LSB.

Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC

A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy.

Energy-efficient switching scheme for SAR ADC with only two reference voltages

An energy-efficient switching method for successive approximation register analog to digital converter is presented in this letter. The proposed two-step switching scheme using the goblet architecture achieves 99.52% less switching energy and 21.09% area reduction over the conventional switching scheme. Moreover, owing to the application of the goblet architecture, the proposed scheme employs only two reference voltages without any requirements for stability or accuracy of the third voltage level.

A highly energy-efficient switching scheme for SAR ADC with the redundant capacitance splitting technology

In this letter, a highly energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) is presented with the redundant capacitance splitting technology. The redundant capacitance splitting technology is put forward innovatively to divide the convert cycles into two parts: high bits cycles and low bits cycles. And through a simple switch, the redundant capacitance is split off from the capacitance array in the high bits convert cycles, resulting in the improvement of SAR ADC performance. With the monotonic mode, the first bit cycle and the second bit cycle are completed without consuming any switching energy. The proposed novel switching scheme can achieve 99.54% less switching energy and 75% reduction in capacitor area compared with the conventional switching scheme for SAR ADC, respectively.

A 10-Bit Differential Ultra-Low-Power SAR ADC with an Enhanced MSB Capacitor-Split Switching Technique

A fully differential energy-efficient switching scheme for binary-weighted capacitor digital-to-analog converter (DAC) is presented. It is observed that the proposed switching scheme reduces energy consumption of DAC by 97% and the capacitance area by 50% over the conventional ones. The effect of supply and common mode voltage variations on the linearity of successive approximation register (SAR) analog-to-digital converter (ADC) is reduced. Moreover, with this switching scheme, one can achieve the same dynamic range as the conventional one, with half the supply voltage as compared to the existing schemes. This makes the proposed switching method suitable for ultra-low-voltage SAR ADCs, which are widely used in biomedical applications. The proposed method is modelled using MATLAB. The results show that the nonlinearity (INL and DNL) caused by capacitor mismatch is reduced. The circuit-level implementation of 10-bit SAR ADC is simulated using UMC 90nm CMOS 1P9M process technology.

Energy-efficient switching scheme based on floating technique for SAR ADC

A high energy-efficiency capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters is proposed in the paper. During the design procedure, the charge characteristic of the floating capacitor and the technique of splitting capacitor ensure zero energy consumption of switching operation. With the reset energy of capacitor arrays taken into account, the proposed switching scheme can achieve 100% less switching energy over the conventional switching scheme. Furthermore, this work also achieves about 50% area reduction with only two reference voltages. The behavioral simulation of the proposed SAR was performed, the maximum differential nonlinearity and maximum integral nonlinearity are 0.451 and 0.452 LSB respectively.

A high-speed, high-linearity, and energy-efficient subranging single-side capacitor switching scheme for SAR ADCs

This paper presents a high-speed, high-linearity, and energy-efficient subranging single-side capacitor switching scheme for successive approximation register analog-to-digital converters. The presented capacitor switching scheme employs a subrange stage to resolve the first few bits, which are adopted by the proposed single-side-based detect-and-skip switching algorithm in the main stage. Compared with conventional architecture, the proposed switching algorithm achieves a 98.0% less switching energy, a 72.5% smaller area, a 38.1% faster comparison process, and a 38.4% less comparator energy consumption.

Energy-Efficient and Area-Saving Asymmetric Capacitor Switching Scheme for SAR ADCs

An asymmetric architecture and energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) are proposed. The novel architecture achieves 81.25% reduction in capacitor area over the convention SAR. With the third reference voltage VCM and split-MSB switching procedure, the proposed switching scheme achieves 99.01% less switching energy over the convention SAR. Besides the significant energy saving, this asymmetric capacitor architecture also obtains a good performance in nonlinearity simulation. Based on the Matlab simulation for capacitor mismatch, the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.166LSB and 0.122LSB, respectively.

An Energy-Efficient Switching Scheme for Low-Power SAR ADC Design

A novel energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) is proposed in this paper. The average switching energy of the proposed switching scheme can be reduced by 95.3%, compared with the [Formula: see text]-based scheme. Moreover, the linearity has been also improved significantly. Employing the proposed switching scheme, a 10-bit 100[Formula: see text]kS/s SAR ADC is designed in SMIC 0.18-[Formula: see text]m CMOS process. At a 0.6-V supply, the ADC consumes 43.7[Formula: see text]nW. Consequently, the figure-of-merit (FOM) is optimized to 0.58[Formula: see text]fJ/conversion-step.

A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference [Formula: see text] for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 [Formula: see text], resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.

Energy-efficient, area-efficient, high-accuracy and low-complexity switching scheme for SAR ADC

Energy-efficient, area-efficient, high-accuracy and low-complexity switching scheme for SAR ADC

Closed‐loop charge recycling switching scheme for SAR ADC

An energy-efficient switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. Based on closed-loop charge recycling method, the proposed switching scheme achieves 100% less switching energy over the conventional switching scheme. Furthermore, the common-mode voltage of the comparator is always V cm and only two reference voltages are used.

Low-Power High-Linearity Switching Procedure for Charge-Redistribution SAR ADC

An energy-efficient capacitive switching scheme in successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed for biomedical applications. With novel sequence initialization and by reducing the up-switching steps during the A/D conversion, the average switching energy of this proposed procedure is reduced by over 98.7% compared with the conventional architecture after taking the parasitic capacitance into consideration. The number of capacitors in the proposed capacitor array is just 1/4 of that in the conventional switching scheme. Moreover, behavioral simulation performed in MATLAB for the 10-bit SAR ADC shows that the linearity performance of this proposed switching scheme is much better than that of previous architectures.

Energy-efficient common-mode voltage switching scheme for SAR ADCs

An energy-efficient switching scheme with common-mode voltage variation in 1LSB for successive approximation register analogue-to-digital converters is proposed. Based on the two-step architecture,...

Trade-off between energy and linearity switching scheme for SAR ADC

A high linearity energy-efficient switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. Monotonic switching scheme and split-capacitor technique are combined. This scheme has no reset energy consumption, and achieves purely 98.05 % less switching energy and 75 % reduction of the total capacitance over the conventional architecture. Moreover, the proposed scheme also improves the linearity of SAR ADC. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.116LSB and 0.083LSB, respectively. The proposed scheme achieves a well trade-off between energy and linearity.

Energy‐efficient switching scheme in SAR ADC for biomedical electronics

An energy-efficient switching scheme for a low-power successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. Taking the parasitic capacitance of the capacitor array into consideration, the average switching energy of the proposed scheme can be reduced by 97.4% compared with the conventional architecture. The proposed scheme also reduces the number of capacitors in the capacitor array by 75.5% and hence achieves area efficiency with high performance.

Energy-efficient and area-efficient switching scheme based on multi-reference for SAR ADC

Energy-efficient and area-efficient switching scheme based on multi-reference for SAR ADC

Energy-efficient and reference-free monotonic capacitor switching scheme with fewest switches for SAR ADC

Energy-efficient and reference-free monotonic capacitor switching scheme with fewest switches for SAR ADC

An Energy-efficient Switching Scheme with Reduced Switching Transients for a Wind-driven Induction Generator

This article presents a scheme for improving the power output of grid-connected induction generator commonly used in wind energy conversion systems. Generally, the stator of the induction generator is connected in a star with a line voltage of √3 times the rated winding voltage to reduce the line current and, hence, conductor size. To extend the generating operation over a wider speed range, delta-star switchable stator windings are also in vogue. In such cases, the stator is star connected in the lower speed range and switched to a delta connection above a threshold speed. In this study, a new switching scheme is proposed wherein the stator coils are always connected in a star, while the stator is connected to different voltages in low- and high-speed conditions. At low wind speeds, nominal winding voltage is applied to the stator, whereas at higher speeds, the stator applied voltage is √3 times higher than the rated winding voltage. The efficacy of the scheme is demonstrated experimentally with a suitable microcontroller-based switching arrangement. Typical results indicate an increase in output with reduced switching transients. A case study on a 3-Φ, 50-kW induction generator is presented to emphasize the performance improvement with the proposed scheme.

23 µW 8.9‐effective number of bit 1.1 MS/s successive approximation register analog‐to‐digital converter with an energy‐efficient digital‐to‐analog converter switching scheme

This study presents a successive approximation register analog-to-digital converter with an energy-efficient switching scheme. A split-most significant bit capacitor array is used with a least significant bit-down switching scheme. Compared with the conventional binary-weighted capacitor array, it reduces the area and average switching energy by 50 and 87% under the same unit capacitor. Moreover, capacitor matching requirement is relaxed by 75%. A prototype design was fabricated in a 0.13 µm complementary metal oxide semiconductor process. It consumes 23.2 µW under 1 V analog supply and 0.5 V digital supply. Measured results show a peak signal-to-distortion-and-noise ratio of 55.2 dB and an effective resolution bandwidth up to 1.1 MHz when it operates at 1.1 MS/s. Its figure-of-merit is 44.1 fJ/conversion-step.