Energy-efficient Circuits Research Articles

A reference-free 7-bit 500 MS/s pipeline ADC using current-mode reference shifting and quantizers with built-in thresholds

The pursuit for energy and area efficient circuits has become greater than ever. Low power and small area integrated circuits are in high demand today. Reference voltage circuitry for analog-to-digital conversion comprises 20---30 % of the overall power and area of the ADC. To this end, a fully differential 1.5-bit multiplying digital-to-analog converter (MDAC) precluding reference voltages, that can be employed in MDAC-based ADCs, is presented. Reference shifting is performed in current-mode and the gain of two is obtained by associating charged capacitors in series in the opamp's feedback loop, achieving a unity feedback factor. Theoretical analyses of various nonideal effects of the reference shifting and gain of two are presented and confirmed with electrical level simulations. Furthermore, to avoid reference voltages in the local quantizers, an architecture with built-in thresholds is used. A proof of concept 1.5-bit/stage 7-bit 500 MS/s pipeline ADC is designed using the proposed MDAC in a standard digital 0.13 μm CMOS technology. The ADC achieves a peak SNDR and SFDR of 36.1 and 48.7 dB, respectively, while dissipating 12.7 mW from a single 1.2 V supply voltage, and it does not require external reference circuitry.

Experimentally verified inductance extraction and parameter study for superconductive integrated circuit wires crossing ground plane holes

As the complexity of rapid single flux quantum (RSFQ) circuits increases, both current and power consumption of the circuits become important design criteria. Various new concepts such as inductive biasing for energy efficient RSFQ circuits and inductively coupled RSFQ cells for current recycling have been proposed to overcome increasingly severe design problems. Both of these techniques use ground plane holes to increase the inductance or coupling factor of superconducting integrated circuit wires. New design tools are consequently required to handle the new topographies. One important issue in such circuit design is the accurate calculation of networks of inductances even in the presence of finite holes in the ground plane. We show how a fast network extraction method using InductEx, which is a pre- and post-processor for the magnetoquasistatic field solver FastHenry, is used to calculate the inductances of a set of SQUIDs (superconducting quantum interference devices) with ground plane holes of different sizes. The results are compared to measurements of physical structures fabricated with the IPHT Jena 1 kA cm−2 RSFQ niobium process to verify accuracy. We then do a parameter study and derive empirical equations for fast and useful estimation of the inductance of wires surrounded by ground plane holes. We also investigate practical circuits and show excellent accuracy.

Design of Near-Threshold CMOS Logic Gates

Numerous efforts have made to balance the tradeoff between power consumption, area and speed of a design. While studying the design at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end and high performance with power within limit at the other has not made. One solution to achieve the ultra-low power consumption is to operate the design in subthreshold region. The use of sub-threshold circuit designing in fast and energy efficient circuits is always needed in electronics industry especially in DSP, image processing and arithmetic units in microprocessors, where the low power is the primary concern and the delay can be tolerated. We design a simple CMOS inverter in weak inversion region (sub-threshold) and compare the power consumption with strong inversion region using Cadence 0.18µm Technology.

Novel Modulation Techniques and Circuits for Transceivers in Body Sensor Networks

Novel energy-efficient modulation technique and circuits for transceivers operating in body sensor networks (BSNs) are described and investigated. They are obtained as a result of the development of differential binary phase shift keying (DBPSK) and named alternating quadratures DBPSK (AQ-DBPSK). While keeping the noise immunity and simplicity of synchronization and realization of DBPSK, AQ-DBPSK increases the efficiency of the transmitter power utilization by dB and radically improves tolerance to frequency offsets between the receivers and corresponding transmitters. The approach used in the development of AQ-DBPSK can also be used for developing novel spreading and despreading techniques and circuits.

Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue)

The three invited and 17 regular papers in this special issue focus on advances in design of energy-efficient circuits and systems. This is the second consecutive issue dedicated to this topic.

Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (First Issue)

The twelve papers in this first issue on advances in design of energy-efficient circuits and systems cover a number of topics, including thermal -aware-design, energy-efficient and low-power design, and ultra-low voltage design techniques for minimum power consumption.

Introduction to the Issue on Green Photonics

The 21 papers in this issue on green photonics cover these broad technical areas: energy-efficient networks and architectures; photonics and electronic technologies for energy-efficient signal processing; optics for energy-efficient router and network design; technologies for energy-efficient optical circuit, burst, and packet switching; novel network paradigms leading to significant energy reduction; photonic and electronics for low-power interconnects; scaling efficiencies enabled by power-aware photonic and electronic-integrated circuits; and current and future trends in energy consumption of ICT and networks.

Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation

We present a design methodology towards minimum-area maximum-performance designs in sub-/ near-threshold operation. Our methodology is based on a new metric called performance-per-area. Unlike conventional gate sizing, we use forward body biasing at synthesis time to render faster, smaller and more energy-efficient circuits. Our theory introduces body biasing into delay and energy models in the form of nonlinear derating functions that can easily be fitted to a technology node. The methodology is validated using an industrial microprocessor consisting of approximately 31 K gates and 3.7 K flip-flops in CMOS 90 nm. We obtain 4.2x better EDP, 3.8x higher speed and 9% smaller area than the non-body-biased counterpart.

A Novel Sensing Method and Sensing Algorithm Development for a Ubiquitous Network

This paper proposes a novel technique which provides energy efficient circuit design for sensors networks. The overall system presented requires a minimum number of independently communicating sensors and sub-circuits which enable it to reduce the power consumption by setting unused sensors to idle. This technique reduces hardware requirements, time and interconnection problems with a supervisory control. Our proposed algorithm, which hands over the controls to two software mangers for the sensing and moving subsystems can greatly improve the overall system performance. Based on the experimental results, we observed that our system, which is using sensing and moving managers, the four sensors required only 3.4 mW power consumption when a robot arm is moved a total distance of 17 cm. This system is designed for robot applications but could be implemented to many other human environments such as “ubiquitous cities”, “smart homes”, etc.

Energy dissipation and transport in nanoscale devices

Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (∼10−8 W) to massive data centers (∼109 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces.

Technical Obstacles to Thin Film Transistor Circuits on Plastic

Two main technical obstacles must be overcome to build a fruitful business in the nascent flexible microelectronics industry: the self-heating effect of thin film transistors (TFTs), and the thermal and mechanical durability of flexible devices. The self-heating effect is controlled through TFT shape, TFT electrical performance, dimensional reductions, and energy-efficient circuits. Plastic engineering is one of the keys to solving thermal and mechanical durability problems faced by flexible microelectronics devices. Once these obstacles are cleared, TFT circuits on plastic will spawn a new industry and markets for plastic large-scale integrations.

An Energy-Efficient Analog Front-End Circuit for a Sub-1-V Digital Hearing Aid Chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.

Wideband Signal Transmission for Energy-Aware Wireless Communications

In this paper, we discuss the role of physical (PHY) layer in realization of energy-aware wireless communication systems. With an energy consumption model for a wireless link between a transmitter and a receiver, we discuss a dominant factor to reduce energy consumption and show that, to reduce energy consumption, we should adopt an energy-efficient circuit architecture and modulation/detection scheme, even allowing a little degradation of packet error rate. Finally, we show that wide band signal transmission has a potential to realize not only high data rate transmission but also low energy consumption in wireless communication systems.

Computational simulations of the total cavo-pulmonary connection: insights in optimizing numerical solutions

The Fontan procedure is a palliative surgical technique that is used to treat patients with congenital heart defects that include complex lesions such as those with a hypoplastic ventricle. In vitro, in vivo, and computational models of a set of modifications to the Fontan procedure, called the total cavopulmonary connection (TCPC), have been developed. Using these modeling methods, attempts have been made at finding the most energy efficient TCPC circuit. Computational modeling has distinct advantages to other modeling methods. However, discrepancies have been found in validation studies of TCPC computational models. There is little in the literature available to help explain and correct for such discrepancies. Differences in computational results can occur when choosing between steady flow versus transient flow numerical solvers. In this study transient flow solver results were shown to be more consistent with results from previous TCPC in vitro experiments. Using a transient flow solver we found complex fluctuating flow patterns can exist with steady inflow boundary conditions in computational models of the TCPC. To date such findings have not been reported in the literature. Furthermore, our computational modeling results suggest fluctuating flow patterns as well as the magnitudes of these secondary flow structures diminish if the TCPC offset between vena cavae is increased or if flanged connections are added. An association was found between these modifications and improvements in TCPC circuit flow efficiencies. In summary, development of accurate computational simulations in the validation process is critical to efforts in finding the most efficient TCPC circuits, efforts aimed at potentially improving the long term outcome for Fontan patients.

0.8 V CMOS adiabatic differential switch logic circuit using bootstrap technique for low-voltage low-power VLSI

A novel 0.8 V CMOS adiabatic differential switch logic (ADSL) circuit using the bootstrap technique for low-voltage low-power VLSI is reported. Using capacitance coupling effects from the bootstrap transistors with the related isolating transistors, this 0.8 VADSL circuit has a 52% smaller propagation delay time, consuming 26% less power as compared to the energy efficient logic circuit.

Adiabatic carry look-ahead adder with efficient power clock generator

Performance and characteristics of an adiabatic logic family are studied and compared with those of combinational and pipelined static CMOS counterparts. An 8-bit adiabatic carry look-ahead adder and its combinational and pipelined static CMOS counterparts are designed using a 0.6-µm CMOS technology. The performance of each circuit is studied in terms of the maximum frequency of operation, the minimum voltage of operation, the circuit energy consumption, and the switching noise generated by the circuit. Based on the simulation results, depending on the operating frequency, the adiabatic adder exhibits energy savings up to 87% compared with its combinational and pipelined static CMOS counterparts. It also exhibits a considerable reduction in switching noise, compared with its static CMOS counterparts. Practical issues in the design of power clock generators needed by adiabatic logic circuits are also explained. Synchronous and asynchronous power clock generators are designed and the more energy efficient circuit for the power clock generation is determined. The power clock generator exhibits a conversion efficiency of 77% at 10 MHz operating frequency.

A centralized hydraulic system for passenger cars

The majority of passenger vehicles use separate hydraulic circuits to drive and control high-power components such as the braking and steering systems. While this approach is acceptable, it is possible for significant improvements in effficiency to be achieved using a centralized system. In order to establish the advantages and disadvantages of the distributed and centralized approaches, a simulation-based feasibility study of the pressure, flow and power requirements of the individual engine cooling, anti-lock braking system (ABS), semi-automatic transmission, active roll control and power assisted steering subsystems was carried out. Using a realistic drive and load cycle together with simulation models accounting for component non-linearities and dynamics, the flow requirements of an integrated hydraulic system were established. It was shown that the steering and roll control suspension requirements were complementary. The steering system requires high flow at low forward speeds, while the suspension requires high flow during conditions of high speed. In addition it was shown that, although the peak flow requirements of an integrated system were high, the mean flow was moderate and the high demands could be met using small accumulator units, suggesting that the system would be feasible for use in passenger cars. Finally, an energy efficient integrated hydraulic circuit including some degree of safety back-up is proposed.

1.5 V CMOS full-swing energy efficient logic (EEL) circuit suitable for low-voltage and low-power VLSI applications

A 1.5 V full-swing energy efficient logic circuit is reported that is suitable for next-generation low-power VLSI applications using a low supply voltage. At 25 MHz and at 1.5 V, the power consumption of the EEL circuit is 70% of that for an ECRL circuit and 47% of that for the static circuit.

A Unified Approach to Submicron DC MOS Transistor Modeling for Low-Voltage ICs

A unified single-equation approach for the MOS transistor drain current modeling for energy-efficient submicron MOS circuits is presented. Instead of three sets of separate equations for the triode, saturation, and weak inversion regions, only a continuous expression which is valid to describe the behavior of drain current and the derivatives in all operation regions can be realized by using a combination of hyperbola, sigmoid, and interpolation methods. The model expression can predict accurate results for the current, output conductance, and transconductance with continuous and smooth characteristics. The simulation results agree well with experimental data.

Design and optimization of a low DC offset CMOS current-source dedicated to implantable miniaturized stimulators

The main goal of our study is the design of a current-source (CS) based on a miniaturized digital-toanalog converter (DAC). The primary application of this device is a wide range of neuromuscular implantable microstimulators. A great deal of attention was devoted to creating a flexible, compact, and energy efficient circuit. A new design method based on an optimization process involving area and linearity is thus proposed. Circuits obtained using this technique were characterized as having a 5-bit DAC resolution, with 2 mA peak output current, while requiring around 0.01 mm2 of chip area, using a 1.2 μm CMOS technology. This paper also extends the method to create an improved current-source, designed to minimize the output DC offset and charge accumulation that are noxious for the stimulated neuromuscular tissues. Our analysis of the proposed circuit configuration show that we can reach a small DC offset error, without using any coupling capacitor, which tend to be bulky, and not desirable in highly miniaturized implants.