Endurance Characteristics Research Articles

Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure

The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device.

Reply to Giannakos, K. Comment on: Toughness of Railroad Concrete Crossties with Holes and Web Openings. Infrastructures 2017, 2, 3

This paper responds to the discussion [1] by Dr. K. Giannakos over our technical note [2].[...]

Enhanced resistive switching characteristics in Pt/BaTiO3/ITO structures through insertion of HfO2:Al2O3 (HAO) dielectric thin layer

An enhanced resistive switching (RS) effect is observed in Pt/BaTiO3(BTO)/ITO ferroelectric structures when a thin HfO2:Al2O3 (HAO) dielectric layer is inserted between Pt and BTO. The P-E hysteresis loops reveal the ferroelectric nature of both Pt/BTO/ITO and Pt/HAO/BTO/ITO structures. The relation between the RS and the polarization reversal is investigated at various temperatures in the Pt/HAO/BTO/ITO structure. It is found that the polarization reversal induces a barrier variation in the Pt/HAO/BTO interface and causes enhanced RS, which is suppressed at Curie temperature (Tc = 140 °C). Furthermore, the Pt/HAO/BTO/ITO structures show promising endurance characteristics, with a RS ratio >103 after 109 switching cycles, that make them potential candidates for resistive switching memory devices. By combining ferroelectric and dielectric layers this work provides an efficient way for developing highly efficient ferroelectric-based RS memory devices.

Confining Cation Injection to Enhance CBRAM Performance by Nanopore Graphene Layer.

Conductive-bridge random access memory (CBRAM) is considered a strong contender of the next-generation nonvolatile memory technology. Resistive switching (RS) behavior in CBRAM is decided by the formation/dissolution of nanoscale conductive filament (CF) inside RS layer based on the cation injection from active electrode and their electrochemical reactions. Remarkably, RS is actually a localized behavior, however, cation injects from the whole area of active electrode into RS layer supplying excessive cation beyond the requirement of CF formation, leading to deterioration of device uniformity and reliability. Here, an effective method is proposed to localize cation injection into RS layer through the nanohole of inserted ion barrier between active electrode and RS layer. Taking an impermeable monolayer graphene as ion barrier, conductive atomic force microscopy results directly confirm that CF formation is confined through the nanohole of graphene due to the localized cation injection. Compared with the typical Cu/HfO2 /Pt CBRAM device, the novel Cu/nanohole-graphene/HfO2 /Pt device shows improvement of uniformity, endurance, and retention characteristics, because the cation injection is limited by the nanohole graphene. Scaling the nanohole of ion barrier down to several nanometers, the single-CF-based CBRAM device with high performance is expected to achieve by confining the cation injection at the atomic scale.

Physical and electrical properties of flash memory devices with nickel oxide(NiO2) charge trapping layer

In this study, we proposed a metal-oxide high-k-oxide-silicon (MOHOS) memory device using a nickel oxide film as the charge trapping layer, and studied the effect of post-deposition rapid thermal annealing (RTA) on the physical and electrical properties. The physical properties were investigated via multiple material analysis techniques such as X-ray diffraction and atomic force microscopy. The optimal annealing temperature for depositing the charge trapping layer was determined through a thorough investigation of the memory window, program/erase (P/E) cycle, crystalline structure, and material composition. Compared to the as-deposited NiO2 film, a MOHOS-type memory device annealed at 900 °C in a nitrogen atmosphere exhibited improved memory characteristics, in terms of a larger window in the capacitance-voltage hysteresis, better data retention (lower charge loss of 11%), faster program and erase cycles, and endurance characteristics (104 P/E cycles) without any significant drift in the flat band voltage. Therefore, the MOHOS memory device with a NiO2 trapping layer is a very promising candidate for future memory device applications.

Conception of Stretchable Resistive Memory Devices Based on Nanostructure‐Controlled Carbohydrate‐block‐Polyisoprene Block Copolymers

It is discovered that the memory‐type behaviors of novel carbohydrate‐block‐polyisoprene (MH‐b‐PI) block copolymers‐based devices, including write‐once‐read‐many‐times, Flash, and dynamic‐random‐access‐memory, can be easily controlled by the self‐assembly nanostructures (vertical cylinder, horizontal cylinder, and order‐packed sphere), in which the MH and PI blocks, respectively, provide the charge‐trapping and stretchable function. With increasing the flexible PI block length, the stretchability of the designed copolymers can be significantly improved up to 100% without forming cracks. Thus, intrinsically stretchable resistive memory devices (polydimethylsiloxane(PDMS)/carbon nanotubes(CNTs)/MH‐b‐PI thin film/Al) using the MH‐b‐PI thin film as an active layer is successfully fabricated and that using the MH‐b‐PI12.6k under 100% strain exhibits an excellent ON/OFF current ratio of over 106 (reading at −1 V) with stable V set around −2 V. Furthermore, the endurance characteristics can be maintained over 500 cycles upon 40% strain. This work establishes and represents a novel avenue for the design of green carbohydrate‐derived and stretchable memory materials.

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

A type of p-channel fin-on-insulator (FOI) FinFET charge trapping memory devices with HfO2 charge trapping layer, Al2O3 tunneling layer and blocking layers along with [TiN/W] metal gate (Metal/Al2O3/HfO2/Al2O3/Si, named as MAHAS in short) have been successfully fabricated. It is found that the new non-volatile memory, named in FOI-MAHAS memory shows better performance as compared with counterparts reported earlier owing to the adoption of p-type FOI channel and specific high-κ dielectrics. The static DC electrical characteristics of the fabricated memory devices including threshold voltage, subthreshold slope, gate breakdown voltage (BVg), source-drain breakdown voltage (BVDS) and memory characteristics such as program/erase (P/E) speed, memory window, endurance, and data retention at room temperature with different P/E approaches have been systematically investigated. A larger memory window, lower P/E voltages, improved P/E speed, as well as good data retention and endurance characteristics with band-to-band hot-electron (BBHE) programming are experimentally obtained. The developed p-channel FOI-MAHAS charge trapping memory is promising for the future nano-scaled NOR-type flash memory applications.

Communication—Effect of a Self-Limited Reset Operation on the Reset Breakdown Characteristics of a Monolithically Integrated 1T1R RRAM

The reset breakdown of resistive random access memory (RRAM) significantly degrades device endurance. We suppressed reset breakdown by optimizing the reset operation in an HfO2-based 1T1R RRAM device. The effective gate-to-source voltage VGSeff is reduced by increasing the RRAM resistance during the reset operation. By applying the optimum VGS, we can both guarantee a sufficient reset current and suppress reset breakdown. The experimental results confirmed improved endurance characteristics without a degraded resistance ratio.

Detection of resistive switching behavior based on the Al2O3/ZnO/Al2O3 structure with alumina buffers

The single ZnO layer and a sandwich Al2O3/ZnO/Al2O3 structure were prepared via atomic layer deposition, and the single ZnO layer showed a feature of ohmic conduction only. When we added that together with top and bottom alumina buffers, a non-polar resistive switching (RS) behavior was accomplished, allowing investigation of its electric endurance and retention characteristics. Analysis of the conduction mechanism at both high and low resistance states using auxiliary mathematic tools resulted in the proposed model of conducting filaments formed in the insulating Al2O3 buffers. The effect of stopping voltage Vend on the resistance window at high resistance state is studied and discussed.

Operation characteristics of Poly-Si nanowire charge-trapping flash memory devices with SiGe and Ge buried channels

Operation characteristics of polycrystalline silicon (poly-Si) nanowire (NW) charge-trapping (CT) flash memory devices with a SiGe and a Ge buried channel are studied and compared in this work. The poly-Si NW devices with a Ge buried channel show faster programming and erasing speeds as compared to those with a SiGe one due to a lower energy barrier in tunneling layer with more Ge composition. The retention and endurance characteristics of devices with a Ge buried channel are similar to those with a SiGe one. Ge buried channel is promising to CT flash device for 3D nonvolatile memory applications.

Unraveling the resistive switching effect in ZnO/0.5Ba(Zr0.2Ti0.8)O3-0.5(Ba0.7Ca0.3)TiO3 heterostructures

This work reports the effect of partial oxygen pressure, used in the deposition of the ZnO layer, on the band alignment at ZnO – 0.5Ba(Zr0.2Ti0.8)O3-0.5(Ba0.7Ca0.3)TiO3 (0.5BZT-0.5BCT) interface and on the resistive switching (RS) behavior of pulsed laser deposited ZnO/0.5BZT-0.5BCT heterostructures. X-ray photoelectron spectroscopy (XPS) has been employed to measure the valence band offset and the conduction band offset of the ZnO/0.5BZT-0.5BCT heterojunctions. The valence and conduction band offsets of the ZnO/0.5BZT-0.5BCT heterostucture with ZnO deposited at 10−2mbar of partial oxygen pressure were found to be 0.27 and 0.80eV, respectively. The RS effect in heterostructures is explained on the base of the charge coupling between the switchable polarization of ferroelectric layer and the non-switchable polarization of semiconductor layer. The heterostructure with ZnO deposited at 10−2mbar of partial oxygen pressure displays optimum RS characteristics, with a switching ratio≥104 and excellent retention and endurance characteristics. The optimum RS characteristics are attributed to a good interface quality with enough carrier concentration in ZnO, as evidenced by XPS.

Effects of Zn doping concentration on resistive switching characteristics in Ag /La1−x Zn x MnO 3 / p + $_{3}/\textit {p}^{\mathrm {+}}$ -Si devices

Ag /La 1 −x Zn x MnO\(_{\mathbf {3}}\boldsymbol {/}\textit {p}^{\boldsymbol {+}}\)-Si devices with different Zn doping contents were fabricated through sol–gel method. The effects of Zn doping concentration on the microstructure of La 1 −x Zn x MnO 3 films, as well as on the resistance switching behaviour and endurance characteristics of Ag /La 1 −x Zn x MnO\(_{\mathbf {3}}\boldsymbol {/}\textit {p}^{\boldsymbol {+}}\)-Si were investigated. After annealing at 600∘C for 1 h, the La 1 −x Zn x MnO 3 (x = 0.1, 0.2, 0.3, 0.4, 0.5) are amorphous and have bipolar resistance characteristics, with R H R S / R L R S ratios >103. However, the endurance characteristics show considerable differences; x= 0 . 3 shows the best endurance characteristics in more than 1000 switching cycles. The conduction mechanism of the Ag /La 1 −x Zn x MnO\(_{\mathbf {3}}\boldsymbol {/}\textit {p}^{\boldsymbol {+}}\)-Si is the Schottky emission mode at high resistance state. However, the conduction mechanism at low resistance state varies with Zn doping concentration. The dominant mechanism at x= 0 . 1 is filamentary conduction mechanism, whereas that at x ≥ 0 . 2 is space-charge-limited current conduction.

Effects of electrode on resistance switching properties of ZnMn2O4 films deposited by magnetron sputtering

ZnMn2O4 films for resistance random access memory (RRAM) were fabricated with different device structures by magnetron sputtering. The effects of electrode on I-V characteristics, resistance switching behavior, endurance and retention characteristics of ZnMn2O4 films were investigated. The ZnMn2O4 films, using p-Si and Pt as bottom electrode, exhibit bipolar resistive switching (BRS) behavior dominated by the space-charge-limited conduction (SCLC) mechanism in the high resistance state (HRS) and the filament conduction mechanism in the low resistance state (LRS), but the ZnMn2O4 films using n-Si as bottom electrodes exhibit both bipolar and unipolar resistive switching behaviors controlled by the Poole-Frenkel (P-F) conduction mechanism in both HRS and LRS. Ag/ZnMn2O4/p-Si device possesses the best endurance and retention characteristics, in which the number of stable repetition switching cycle is over 1000 and the retention time is longer than 106 seconds. However, the highest RHRS/RLRS ratio of 104 and the lowest VON and VOFF of 3.0 V have been observed in Ag/ZnMn2O4/Pt device. Though the Ag/ZnMn2O4/n-Si device also possesses the highest RHRS/RLRS ratio of 104, but the highest values of VON,VOFF, RHRS and RLRS, as well as the poor endurance and retention characteristics.

~3-nm ZnO Nanoislands Deposition and Application in Charge Trapping Memory Grown by Single ALD Step.

Low-dimensional semiconductor nanostructures are of great interest in high performance electronic and photonic devices. ZnO is considered to be a multifunctional material due to its unique properties with potential in various applications. In this work, 3-nm ZnO nanoislands are deposited by Atomic Layer Deposition (ALD) and the electronic properties are characterized by UV-Vis-NIR Spectrophotometer and X-ray Photoelectron Spectroscopy. The results show that the nanostructures show quantum confinement effects in 1D. Moreover, Metal-Oxide-Semiconductor Capacitor (MOSCAP) charge trapping memory devices with ZnO nanoislands charge storage layer are fabricated by a single ALD step and their performances are analyzed. The devices showed a large memory window at low operating voltages with excellent retention and endurance characteristics due to the additional oxygen vacancies in the nanoislands and the deep barrier for the trapped holes due to the reduction in ZnO electron affinity. The results show that the ZnO nanoislands are promising in future low power memory applications.

Unipolar resistive switching behavior of amorphous SrMoO4 thin films deposited at room temperature

Amorphous SrMoO4 (SMO) thin films were deposited on Pt/Ti/SiO2/Si substrates at room temperature by pulsed laser deposition and the resistive switching (RS) behavior of the Au/SMO/Pt devices was investigated. The Au/SMO/Pt devices exhibit typical unipolar RS behavior with excellent switching parameters as follows: high resistance ratio (~105) between the low resistance state (LRS) and high resistance state (HRS), non-overlapping switching voltages, and good endurance and retention characteristics. Detailed analysis of their current-voltage characteristics reveals that the conduction mechanisms are Ohmic conduction in the LRS and lower voltage region of HRS, and Poole-Frenkel emission in the higher voltage region of the HRS. Temperature dependent resistance measurements, combined with x-ray photoelectron spectroscopy and model analysis indicate that the unipolar RS behavior of the Au/SMO/Pt devices could be understood by a conical conducting filaments (CFs) model in which the conical CFs are composed of oxygen vacancies. The conical CFs extend from the cathode to anode during the forming process and the observed RS behavior occurs in the localized region near the anode. These results suggest that the room-temperature- deposited amorphous SMO thin films could find potential application in nonvolatile RS memory.

The Effects of Ultrasonic Nanocrystal Surface Modification Technique Temperature on Microstructure and Wear of Alloy 600

Alloy 600 (UNS N06600) is an austenitic nickel-based alloy with superior corrosion resistance and high-temperature endurance, which determines its widespread applications in aeronautical, aerospace, marine and nuclear industries. Particularly, a number of nuclear components used Alloy 600 as their structure materials due to their high corrosion resistance, high-temperature endurance and excellent fabricant characteristics. Many failures have occurred in Alloy 600 with various forms of environmental degradations during long-term operation. In this study, an ultrasonic nanocrystal surface modification (UNSM) technique was applied to Alloy 600 at a room and a high temperature of 500 OC. The effects of UNSM treatment temperature on the microstructure and wear behavior including a compressive residual stress were investigated. The hardness, compressive residual stress with respect to depth from the top surface were measured. Also, the wear behavior of UNSM-treated at a room and a high temperature Alloy 600 specimen was compared to that of the untreated specimen. The increase in wear resistance by UNSM technique was discussed in terms of increased hardness, refined grain size and induced compressive residual stress.

Flexible SiInZnO thin film transistor with organic/inorganic hybrid gate dielectric processed at 150 °C

Silicon indium zinc oxide (SIZO) thin film transistors (TFTs) have been fabricated on a flexible polyimide (PI) substrate by using organic/inorganic hybrid gate dielectrics of poly-4vinyl phenol (PVP) and Al2O3. To improve the mechanical stability, Al2O3 has been used as a buffer layer on the flexible substrate. The Al2O3 layer of hybrid gate dielectrics protected the organic gate dielectric and improved mechanical flexibility. The different surface roughness of the gate dielectrics is investigated. The performance of the device with smooth surface roughness was significantly improved. Finally, the electrical characteristics of the TFTs with hybrid gate dielectrics were measured as well as the promising electrical endurance characteristics at the bending radius of 5 mm.

Non-volatile resistive memory device fabricated from CdSe quantum dot embedded in thermally grown In2O3 nanostructure by oblique angle deposition

In this paper we report In2O3/CdSe quantum dot based non-volatile resistive memory device with ON/OFF ratio ∼1000. Indium nanostructures were grown by oblique angle deposition technique in a thermal evaporator. Indium oxide nanostructures had size ranging from 20 nm to 100 nm as observed from TEM and AFM methods. The facile device fabricated with a layer of CdSe quantum dot on indium oxide film exhibited excellent endurance characteristics over 100,000 switching cycles. Retention tests showed good stability for over 4000 s. Memory operating mechanism is proposed based on charge trapping/de-trapping in quantum dots with indium oxide acting as barrier leading to Coulomb blockade. The mechanism is supported by negative differential resistance (NDR) observed exclusively in the ON state.

Nanowire width dependence of data retention and endurance characteristics in nanowire SONOS flash memory

The investigations on the nanowire width (W) dependence of memory performance including P/E (programming and erasing) speed, data retention time and endurance characteristics in nanowire SONOS flash memory have been performed through the measurement and the device simulation. From measured results, a narrow device has advantages in terms of a fast P/E speed and the endurance characteristics. However, a narrow device has disadvantage in terms of the decreased data retention time. Another disadvantage of a narrow device is expected to the large power consumption due to large GIDL (Gate Induced Drain Leakage) current. The device simulation was performed to explore the causes for a fast P/E speed, an enhanced endurance characteristics and the reduced data retention time in narrow devices.

Notice of Violation of IEEE Publication Principles: Overview of Selector Devices for 3-D Stackable Cross Point RRAM Arrays

Cross point RRAM arrays is the emerging area for future memory devices due to their high density, excellent scalability. Sneak path problem is the main disadvantage of cross point structures which needed to be overcome to produce real devices. Various self-rectifying cells like complementary resistive cell, hybrid RRAM cell, valence modulated conductive oxide RRAM and non-linear resistive memory with tunneling barrier, etc., are proposed to overcome the sneak path problem and to achieve the high density with good on/off ratio. However, it is challenging to fabricate the self-rectifying cells operating at low program/erase voltages with high non-linearity for both read and write operations and exhibiting good retention and endurance characteristics at the same time for a single device. 1S1R devices are more attractive than SRC due to large optimization possibilities to obtain better device performance as they have separate selector cell and memory cell which decouples the control parameters. Various kinds of selector devices like Si-based selector, metal-oxide based selector, threshold switch selector, mixed ionic-electronic conduction selector etc., are under intense research to obtain the best performance cross point memory devices. In this paper, we have briefly discussed about recent progress on various self-rectifying cells and selector devices for obtaining 3-D stackable cross point memory arrays.