TiSi2 is widely used as contact, gate and interconnect material in high-performance metal-oxide-semiconductor (MOS) devices because of its low resistivity (15±20 iU-cm) [1], high-temperature stability and ` self-aligned'' properties [2, 3]. The rapid scaling in device dimensions necessitates the use of low resistivity materials for interconnects and also for back-end metallization. The implementation of the Ti self-aligned silicide (SALICIDE) process becomes increasingly dif®cult, however, especially at the deep sub-micron regime as a result of the well-known ` ®neline effect'' [4, 5]. Hiroshi [6] reported that lowleakage and low-resistance sub-micron silicided complimentary metal oxide semiconductor (CMOS) devices are achievable through Ti SALICIDE technology with recoil nitrogen ions, which were introduced through a contamination-restrained, oxygen-free, lowpressure, chemical-vapor-deposited nitride layer. In this work, we directly implanted nitrogen ion (N) to understand the bulk effects of deeply implanted nitrogen. Cross-sectional transmission electron microscopy (XTEM) analysis was performed to investigate the changes associated with N implantation in the Ti SALICIDE process and to relate these changes to the electrical properties observed. In this experiment, a p-type (1 0 0)-oriented silicon wafer was used as the substrate for device fabrication. Nitrogen ions (N) with 5 3 10 ions cmy2 dosage and 80 keV energy were introduced through ion implantation. The projected range (Rp) of the N implantation was about 0.2 im based on transport of ions in matter (TRIM) 90 simulations. Subsequently, a single layer of 70 nm Ti was deposited by physical vapor deposition (PVD) followed by a ®rst rapid thermal anneal (RTA) at 690 8C and second RTA at 850 8C to form the ®nal C-54 phase TiSi2 ®lm. Fig. 1 is a XTEM image of the control specimen, i.e., without N ion implantation. The thickness of the C-54 TiSi2 ®lm is about 91 nm. No signi®cant defects were observed in this specimen. For the Nimplanted specimen, we observed (1) a thicker C-54 phase TiSi2 ®lm on the narrow poly-Si gate, (2) defects near the spacer and ®eld oxide and (3) two layers of end-of-range (EOR) defect in the underlying Si substrate. All these observed abnormalities are likely to in uence the device performance.