Enclosed Layout Transistors Research Articles

Aspect Ratio Modeling of Radiation-Hardened 8-Shape Enclosed Layout Transistor

The leakage current caused by the total ionizing dose (TID) effect remains a challenge for deep submicron technologies. The enclosed layout transistor (ELT) NMOS using the radiation hardening by design (RHBD) technique has a great potential for TID radiation hardening. Compared with the b-shape ELT that has a clear limitation on its aspect ratio, 8-shape ELT is preferable in the circuit design. The aspect ratio modeling of 8-shape ELT is proposed in this work for the first time. The basic principle is based on the 8-shape ELT equivalent circuit, composing one main transistor and two edge transistors. In accordance with the Sentaurus simulation result, the equivalent trapezium approximation is made for the edge transistor. A semi-empirical parameter is given to calculate the proposed model. The model is verified by the comparison between measured results of the fabricated 8-shape ELT in 180nm CMOS process and the pure calculation results. A further discussion is made to improve the accuracy of the proposed model, which is approved by the comparison between different models in previous work. Some modifications are also made to adjust the 8-shape ELT before the application.

Source Switched Charge-Pump PLLs for High-Dose Radiation Environments

This paper presents a radiation tolerant charge-pump Phase-Locked Loop (PLL) with low static phase error variability suitable for high-performance clock systems in high-dose radiation environments. We investigate the use of source switching charge-pump architectures to minimize any voltage-or dose-dependent charge injection and address the limitations of Enclosed Layout Transistors (ELTs) in the conventional drain switched charge-pump. The circuit has been processed in a 65nm Complementary Metal Oxide Semiconductor (CMOS) technology and has been experimentally verified with X-rays up to a total ionizing dose of 180 Mrad.

Pseudo-Symmetric Enclosed Layout Transistors for Radiation Hardened Analog Applications

The enclosed layout transistor is an alternative to reduce the radiation sensitivity of CMOS devices by avoiding thick field oxide paths between source and drain terminals. This prevents the increase of leakage current of devices working under radiation. The commonly adopted square geometry of this design brings asymmetry between source and drain, modifying characteristics such as output conductance and capacitance, if compared to a traditional layout. Therefore, considering analog designs, this may complicate the process of mapping a non-hardened design onto a radiation tolerant version, even if the aspect ratios ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$W/L$</tex-math></inline-formula> ) of the transistors are designed to be the same. In this paper, we propose a pseudo-symmetric version of enclosed layout devices in order to better approximate its electrical characteristics to the conventional layout style. This way, no significant modification on simulation and design validation flow is necessary. The devices were fabricated in a 130 nm process, being then characterized and compared with regular (non-symmetric) ELTs as well as to conventional (two-edge) layout transistors. Results show a good agreement between the tested parameters of the pseudo-symmetric ELTs and the correspondent two-edge devices.

A 15 V-Tolerant and Radiation-Hardened MOSFET Driver With Positive and Negative References

Radiation-hardened and high-voltage power circuits are key components in aerospace applications. However, when working at high voltages, the effects of the total ionizing dose (TID) and the single event limit the application of power driving circuits in a radiation environment. A 15 V-tolerant radiation-hardened MOSFET driver was designed. The circuit architecture, which is based on positive and negative references, can reduce the gate source voltage of the transistors to less than 5&#x00A0;V, allowing the selection of thin-gate oxide high-voltage transistors. On this basis, adopting enclosed layout transistor (ELT) N-channel metal oxide semiconductor (NMOS) transistors helps the driver to obtain a good resilience to TID hardness. Additionally, this work optimized the layout of high-voltage N-type laterally diffused metal oxide semiconductor (LDMOS) transistors in the driver to effectively improve the single-event burnout (SEB) threshold. Three chips with different N-type drift region lengths were designed and fabricated in a 0.35&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu m$</tex-math></inline-formula> BCD process. The test results showed that the TID hardening capability of these chips with ZENER references and ELT NMOS transistors all exceeded 100 krad (Si). In addition, this driver was tested under heavy ion irradiation with linear energy transfer (LET) exceeding 75 MeV&#x00B7;<inline-formula><tex-math notation="LaTeX">$\dot\mathrm{{c}}{\mathrm{{m}}^{2}}\mathrm{{/mg}}$</tex-math></inline-formula>. The results show that this driver with a 6.6&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu m$</tex-math></inline-formula> drift region length had no single event latchup (SEL), single event gate rupture (SEGR), or single event burnout (SEB) sensitivity.

L Style n-MOSFET Layout For Mitigating TID Effects

This paper proposes a new rad hard layout L style of nmos metal oxide semiconductor field effect transistor (n-MOSFET), which is evaluated to show that its efficacy at reducing radiation-induced leakage currents, thus improving the total ionization dose(TID) tolerance with very less area and parasitic capacitance as compared to enclosed layout transistor(ELT). This proposed layout structure is fully compatible to present commercial fabrication technology without any additional mask requirement as compared to conventional n MOSFET fabrication and can be used as radiation tolerant by design technique. The simulated ID - VG characteristics of the rad hard L n-MOSFET layout demonstrated the effectiveness of eliminating radiation-induced leakage current paths. The leakage current in proposed rad hard L n-MOSFET has been reduced by factor of 108 at 300Krad dose as compared to conventional layout n-MOSFET.

A 112 Gb/s Radiation-Hardened Mid-Board Optical Transceiver in 130-nm SiGe BiCMOS for Intra-Satellite Links

We report the design of a 112 Gb/s radiation-hardened (RH) optical transceiver applicable to intra-satellite optical interconnects. The transceiver chipset comprises a vertical-cavity surface-emitting laser (VCSEL) driver and transimpedance amplifier (TIA) integrated circuits (ICs) with four channels per die, which are adapted for a flip-chip assembly into a mid-board optics (MBO) optical transceiver module. The ICs are designed in the IHP 130 nm SiGe BiCMOS process (SG13RH) leveraging proven robustness in radiation environments and high-speed performance featuring bipolar transistors (HBTs) with fT/fMAX values of up to 250/340 GHz. Besides hardening by technology, radiation-hardened-by-design (RHBD) components are used, including enclosed layout transistors (ELTs) and digital logic cells. We report design features of the ICs and the module, and provide performance data from post-layout simulations. We present radiation evaluation data on analog devices and digital cells, which indicate that the transceiver ICs will reliably operate at typical total ionizing dose (TID) levels and single event latch-up thresholds found in geostationary satellites.

Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors

Aerospace applications are attractive candidates to embed artificial neural networks despite their excellent parallel processing capability and reduced energy consumption. Nonetheless, the long-term exposure to incidence levels of ionizing radiation may degrade their physical components reducing, therefore, their reliability and expected lifetime. Thus, it is mandatory to face the challenge of enhancing the radiation hardening characteristics of a neural circuit before operating in harsh environments. A possible solution to substantially reduce long-term spurious effects caused by ionizing radiation [referred to as total ionizing dose (TID)] is to change the conventional rectangular MOS gate geometry to a nonstandard topology referred to as an enclosed layout transistor (ELT). In the context of hardening a complete neuron circuit against TID effects, together with the well-established ELT paradigm, it is possible to exploit the inclusion of other hardened devices, for instance, the memory element. In this sense, the Oxide-based Resistive Random Access Memory (OxRAM) can be used as the memory element, which is inherently tolerant against ionizing radiation and, hence, better suited for a fully hardened circuit. In this work, we propose to harden the design of an existing OxRAM-based neuron circuit through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the nMOS and pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 180-nm technology, have been carried out to validate our proposed design. In addition, we exploit two simulation setups: first, the OxRAM's behavior in a simple circuit configuration, to provide a better understanding of the OxRAM device; second, the OxRAM-based neuron circuit, to evaluate the behavior of the proposed neuron circuit hardened with ELTs. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications.

Design, Implementation, and Experimental Verification of 5 Gbps, 800 Mrad TID and SEU-Tolerant Optical Modulators Drivers

This paper presents the design and experimental verification of two drivers designed to be compliant with the high radiation dose levels present in the inner layers of the CERN’s Large Hadron Collider (LHC) experimental chambers. The drivers, designed to face up to 800 Mrad (SiO2) Total Ionizing Dose, are able to sustain up to 5 Gbps bit-rate links when integrated in a 65 nm CMOS technology. They are designed to drive two Silicon Photonics optical modulators, Mach Zehnder Modulator and Ring Resonator, which have shown high rad-tolerant levels. The high dose level hardness of the drivers has been achieved by adopting the following Radiation Hardening By Design (RHBD) techniques: enhancement of the MOSFETs model to take into account the effects of high radiation dose levels and of single event effects on the devices, avoidance of using P-MOSFETs, increase of the minimum MOSFET lengths for the switching devices, and the use of Enclosed Layout Transistors shape plus some layout precautions. Moreover, to increase the drivers speed, techniques like buffer chain and inductive peaking are used in the drivers’ design. The experimental results have verified the matching of the high-speed high-voltage constraint required by the application. The Total Ionization Dose tests have shown, at 800 Mrad (SiO2), a 30% and 25% amplitude reduction of the output signals eye diagrams of the Mach Zehnder Modulator driver and of the Ring Resonator driver, respectively. In the worst case, in which the drivers will be placed within 5 cm from the beamline of the CMS experiment of the upgraded LHC, the heavy ions tests have shown a BER of 5.19e-8.

P-Edge NMOSFET for Improving TID Tolerance

This letter proposes a novel device structure named P-edge nMOS, in which high P+ doped belts are placed at the edges of the N+ source and drain. This structure is immune to the radiation-induced edge effects, thus, is able to improve total ionizing dose tolerance with much less area cost than enclosed layout transistors. Furthermore, P-edge nMOS is fully compatible with standard commercial technologies and can be used as a technique of radiation hardened by design. In order to evaluate the radiation tolerance of the new structure, sample transistors fabricated by the SMIC 350-nm commercial CMOS process with shallow trench isolation have been irradiated up to total doses of 2 Mrad(Si). The experimental results show that the leakage current of the P-edge nMOS is four orders of magnitude smaller than the normal nMOS device and the threshold voltage variation of the P-edge nMOS is reduced by about 90% when the dose is up to 2 Mrad(Si). The proposed P-edge nMOS can be a competitive alternative device to be used in CMOS integrated circuits for space applications.

Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library

Ionizing radiation degrades the electrical characteristics of MOS devices, reducing their reliability, performance, and lifetime; therefore, hardening techniques are required for the proper functioning of those devices when exposed to harsh environments. Nonetheless, in the context of design flow automation, necessary to synthesize complex digital circuits, there is a lack of reliable foundry-provided Radiation Hardening by Design (RHBD) cell libraries. In this work, a complete RHBD flow methodology employing enclosed-layout transistors (ELTs) and guard rings, transparent to the designer, and fully compatible with commercial CAD tools and standard fabrication processes is presented. The proposed flow includes the automated calculation of the effective aspect ratio of the ELTs for annular and rectangular topologies, and a template proposal for digital cells, as well as series and parallel arrangements. Moreover, calculation of aspect ratio between pull-up and down networks and output buffers sizing using Logical Effort (LE) methodology, i.e., timing optimization accounting for typical commercial digital design constraints, is considered. Test structures, enclosing single n,pMOS devices, series and parallel arrangements, inverter cells, ring oscillators, and output buffers, were fabricated in two different technology nodes (600 nm and 180 nm). The experimental results were compared to SPICE simulations performed using the models here implemented. The results indicate that the flow methodology is feasible to implement and fully compatible with the CAD tools employed for circuit design. Besides, two case studies were first silicon-proven, presenting fully functional behavior under typical conditions.

Aspect ratio of radiation-hardened MOS transistors

The reliability of electronics in the proximity of the ionizing radiation is a key requirement in particular in high energy physics, nuclear power or space applications. One way to improve robustness of MOS transistors operating in such environments is to use enclosed layout techniques. This special layout approach helps to maintain leakage current of MOS transistors at low level even after irradiation, in contrast to a linear layout MOS transistor, where leakage current could increase by orders of magnitude. The issue, arising with enclosed layout transistors, is related to channel modelling, since the MOS transistor gate geometry is no more a simple rectangle. In this work, modelling of equivalent width and length dimensions of the MOS transistor channel under the gate is addressed. For this purpose transistors of four types and two layout versions, fabricated in a standard 180 nm CMOS process, are characterized. The accuracy of available models for equivalent channel dimensions is analysed, along with a new simplified geometrical model developed by the authors. They are further compared to the empirically extracted aspect ratio. The improvement possibilities for the considered models are then identified.

Performance and simulation accuracy evaluation of analog circuits with enclosed layout transistors

This paper presents an investigation on two important issues related to the application of enclosed layout transistor (ELT) to the design of analog building blocks: the performance impacts, related to the geometrical asymmetry and capacitances of drain and source terminals and the possible errors of commercial design tools when performing the layout versus schematic and layout extraction tasks. A common-source (CS) amplifier is considered as case study, to which the ELT layout technique is applied. SPICE simulations are performed, considering different methodologies to estimate the effective aspect ratio (W/L) of the ELT devices. The extracted equivalent W/L using a commercial design tool is compared with well-known mathematical models presented in the literature. Simulations were carried out considering three different channel lengths for the CS amplifier. The possibility of setting the transistor drain as inner or outer terminal of the ELT was also investigated. According to obtained results, considering a 0.18 µm technology, there may be significant performance differences, both in DC and AC behavior of the amplifier, and significant divergences of the extracted W/L, when compared to the analyzed models. Additionally, in order to improve the achievable aspect ratio range of square ELTs, we propose to use parallel and series associations of enclosed devices. Depending on the desired W/L, it is also possible to save silicon area with such associations.

Electrical study of radiation hard designed HfO2-based 1T-1R RRAM devices

ABSTRACTIn this work the electrical performance of a radiation hard designed 1T-1R resistive random access memory (RRAM) device is investigated in DC (voltage sweep) and AC (pulsed voltage) modes. This new device is based on the combination of an Enclosed Layout Transistor (ELT) used as selector device and a TiN/ HfO2/ Ti/TiN RRAM stack used as resistive device. The high cell to cell variability in the DC mode makes it difficult to define an electrical gap between the High Resistive State (HRS) and the Low Resistive State (LRS). The strong reduction of the variability by the use of Incremental Step Pulse with Verify Algorithm (ISPVA) makes the later a mandatory programming approach. The Quantum Point Contact (QPC) model defines an energy barrier located in the rupture point of the filament in HRS. The compensation between the width and height variations of this barrier during cycling could explain the stability of HRS and LRS. The good performance of the proposed device using the ISPVA programming approach makes it a good candidate for Rad-Hard Non Volatile Memories integration.

A New Test Environment Approach to SEE Detection in MOSFETs

This paper shows a comparison between two different MOSFET structures: a conventional layout (CM) and Diamond (DM - enclosed layout transistor), as tolerance to the Single Event effect - SEE. Both CMOS 0.35μm technology devices types have the same geometric factor (W/L) and during irradiation were monitored continuously to detect and acquire the SEEs applying a new approach with a PXI test system. For this work was used heavy ion beams produced at the São Paulo 8 UD Pelletron accelerator.

Dummy Gate-Assisted n-MOSFET Layout for a Radiation-Tolerant Integrated Circuit

A dummy gate-assisted n-type metal oxide semiconductor field effect transistor (DGA n-MOSFET) layout was evaluated to demonstrate its effectiveness at mitigating radiation-induced leakage currents in a conventional n-MOSFET. In the proposed DGA n-MOSFET layout, radiation-induced leakage currents are settled by isolating both the source and drain from the sidewall oxides using a p+ layer and dummy gates. Moreover, the dummy gates and dummy Metal-1 layers are expected to suppress the charge trapping in the sidewall oxides. The inherent structure of the DGA n-MOSFET supplements the drawbacks of the enclosed layout transistor, which is also proposed in order to improve radiation tolerance characteristics. The V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> -I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> simulation results of the DGA n-MOSFET layout demonstrated the effectiveness of eliminating such radiation-induced leakage current paths. Furthermore, the radiation exposure experimental results obtained with the fabricated DGA n-MOSFET layout also exhibited good performance with regard to the total ionizing dose tolerance.

Radiation hardness studies on CMOS monolithic pixel sensors

This paper presents irradiation studies performed on a CMOS monolithic pixel sensor prototype implementing different optimizations of the pixel cell aimed at a superior radiation tolerance. Irradiations with 200 keV electrons up to a total dose of 1.1 Mrad have been performed in view of the utilization of such a design in Transmission Electron Microscopy (TEM) applications. Comparative irradiations were performed with 29 MeV protons up to a 2 Mrad total dose and with 1–14 MeV neutrons up to fluences in excess of 10 13 n eq cm −2. Experimental results show an improved performance of pixels designed with Enclosed Layout Transistor (ELT) rules and an optimized layout of the charge collecting diodes.

Development of radiation tolerant monolithic active pixel sensors with fast column parallel read-out

Monolithic active pixel sensors (MAPS) [1] (Turchetta et al., 2001) are being developed at IPHC—Strasbourg to equip the EUDET telescope [2] (Haas, 2006) and vertex detectors for future high energy physics experiments, including the STAR upgrade at RHIC [3] (T.S. Collaboration, 2005) and the CBM experiment at FAIR/GSI [4] (Heuser, 2006). High granularity, low material budget and high read-out speed are systematically required for most applications, complemented, for some of them, with high radiation tolerance. A specific column-parallel architecture, implemented in the MIMOSA-22 sensor, was developed to achieve fast read-out MAPS. Previous studies of the front-end architecture integrated in this sensor, which includes in-pixel amplification, have shown that the fixed pattern noise increase consecutive to ionizing radiation can be controlled by means of a negative feedback [5] (Hu-Guo et al., 2008). However, an unexpected rise of the temporal noise was observed. A second version of this chip (MIMOSA-22bis) was produced in order to search for possible improvements of the radiation tolerance, regarding this type of noise. In this prototype, the feedback transistor was tuned in order to mitigate the sensitivity of the pixel to ionizing radiation. The performances of the pixels after irradiation were investigated for two types of feedback transistors: enclosed layout transistor (ELT) [6] (Snoeys et al., 2000) and “standard” transistor with either large or small transconductance. The noise performance of all test structures was studied in various conditions (expected in future experiments) regarding temperature, integration time and ionizing radiation dose. Test results are presented in this paper. Based on these observations, ideas for further improvement of the radiation tolerance of column parallel MAPS are derived.

Analytical model of short-channel gate enclosed transistors using Green functions

Enclosed-layout transistors fabricated in standard CMOS processes are known to offer a natural robustness against radiation effects, a characteristic which is boosted in submicron technologies due to the reduction of the oxide thickness. In this paper, a thorough analytical I–V model of short-channel polygonal enclosed-layout transistors is proposed, addressing the issues of drain-induced barrier lowering and threshold voltage roll-off due to short-channel effects. Experimental data is reported, showing good agreement with the theoretical model.

ECCTD 2007 Special Issue ‘Bridging Technology Innovations to Foundations’

ECCTD 2007 Special Issue ‘<i>Bridging Technology Innovations to Foundations</i>’

ATLAS pixel opto-electronics

We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 μm CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results of the performance of these chips, including irradiation with 24 GeV protons up to 61 Mrad (2.3×10 15 p/cm 2).