Emulation Speed Research Articles

Cytomorphic Electronics With Memristors for Modeling Fundamental Genetic Circuits.

Cytomorphic engineering attempts to study the cellular behavior of biological systems using electronics. As such, it can be considered analogous to the study of neurobiological concepts for neuromorphic engineering applications. To date, digital and analog translinear electronics have commonly been used in the design of cytomorphic circuits; Such circuits could greatly benefit from lowering the area of the digital memory via memristive circuits. In this article, we propose a novel approach that utilizes the Boltzmann-exponential stochastic transport of ionic species through insulators to naturally model the nonlinear and stochastic behavior of biochemical reactions. We first show that two-terminal memristive devices can capture the non-linear and stochastic behavior of biochemical reactions. Then, we present the design of several building blocks based on analog memristive circuits that inherently model the biophysical mechanisms of gene expression. The circuits model induction by small molecules, activation and repression by transcription factors, biological promoters, cooperative binding, and transcriptional and translational regulation of gene expression. Finally, we utilize the building blocks to form complex mixed-signal networks that can simulate the delay-induced oscillator and the p53-mdm2 interaction in the cancer signaling pathway. Our approach can provide a fast and simple emulative framework for studying genetic circuits and arbitrary large-scale biological networks in systems and synthetic biology. Some challenges may be that memristive devices with frequent learning and programming do not have the same longevity as traditional transistor-based electron-transport devices, and operate with significantly slower time constants, which can limit emulation speed.

EFIC-ME: A Fast Emulation Based Fault Injection Control and Monitoring Enhancement

The security and dependability of embedded systems are increasing due to the sensitive and condensed structure of nanodevices. As the chip area shrinks and the technologies upgrade, the probability of Single Event Upset or Multi Bit Upset proliferate which may lead to unexpected results. This article presents a fault-injection tool called EFIC-ME (Emulation based Fault Injection Control and Monitoring Enhancement) using an emulation technique with a reasonable contribution to flexibility and controllability. Existing emulation based fault-injection tools, targeting Field Programmable Gate Arrays (FPGA), reveal high efficiency and low emulation time, but they still lack the control of fault injection time. The proposed tool (EFIC-ME) achieves a low emulation time and provides a sophisticated way to inject the fault in a specific location at a specific clock cycle inside the Design Under Test (DUT). Additionally, it also employs an observability mechanism to monitor the current state of flip-flops on a user defined time. In the context of high emulation speed, it provides an Opal Kelly FPGA interface between the host controller and emulator. In order to evaluate the dependability of the proposed tool, a mechanism has been provided in terms of FoEA (Factors of emulation analysis) and fault injection rate. The FoEA estimates the failure probability of a complete DUT and the failure probability of a specific location inside the DUT which directly affects an output. The designed architecture is initially validated using simulation to verify the functional characteristics. Subsequently, the fault injection campaign has been performed on Kintex-7 FPGA for seven different DUTs. The achieved results have been discussed and compared with state-of-the-art in terms of various performance attributes.

Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA

Modeling and simulation/emulation play a major role in research and development of novel Networks-on-Chip (NoCs). However, conventional software simulators are so slow that studying NoCs for emerging many-core systems with hundreds to thousands of cores is challenging. State-of-the-art FPGA-based NoC emulators have shown great potential in speeding up the NoC simulation, but they cannot emulate large-scale NoCs due to the FPGA capacity constraints. Moreover, emulating large-scale NoCs under synthetic workloads on FPGAs typically requires a large amount of memory and thus involves the use of off-chip memory, which makes the overall design much more complicated and may substantially degrade the emulation speed. This article presents methods for fast and cycle-accurate emulation of NoCs with up to thousands of nodes using a single FPGA. We first describe how to emulate a NoC under a synthetic workload using only FPGA on-chip memory (BRAMs). We next present a novel use of time-division multiplexing where BRAMs are effectively used for emulating a network using a small number of nodes, thereby overcoming the FPGA capacity constraints. We propose methods for emulating both direct and indirect networks, focusing on the commonly used meshes and fat-trees ( k -ary n -trees). This is different from prior work that considers only direct networks. Using the proposed methods, we build a NoC emulator, called FNoC, and demonstrate the emulation of some mesh-based and fat-tree-based NoCs with canonical router architectures. Our evaluation results show that (1) the size of the largest NoC that can be emulated depends on only the FPGA on-chip memory capacity; (2) a mesh-based NoC with 16,384 nodes (128×128 NoC) and a fat-tree-based NoC with 6,144 switch nodes and 4,096 terminal nodes (4-ary 6-tree NoC) can be emulated using a single Virtex-7 FPGA; and (3) when emulating these two NoCs, we achieve, respectively, 5,047× and 232× speedups over BookSim, one of the most widely used software-based NoC simulators, while maintaining the same level of accuracy.

Fast profiling framework and race detection for heterogeneous system

Abstract Heterogeneous computing is a growing trend in recent computer architecture design and is often used to improve the performance and power efficiency for computing applications by utilizing the special-purpose processors or accelerators, such as the Graphic Computing Unit (GPU), Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP). With the increase of complexity, the interaction among accelerators and processors could be deadfall if a race condition happens. However, the existing tools for such task are either too slow or hard to extend the race condition detection mechanism. Therefore, tools for application profiling with approximate timing model are important to the design of such heterogeneous systems in a timing manner. In this paper, we proposed a pluggable GPU interface on an existing timing approximate CPU simulator based on QEMU for analyzing the memory behavior of heterogeneous systems. Monitoring the memory behavior, the pluggable interface could be extended to any kinds of accelerators, such as GPU, DSP and FPGA, for race condition detection. Taking the GPU as an example, we integrated the detailed GPU simulator from Multi2Sim with the existing timing approximate CPU simulator, VPA, to showcase the efficiency of the proposed work. The experimental results showed that the emulation speed of the proposed framework could even reach 9 × faster than Multi2Sim in some cases. In addition, the race condition detection mechanism further indicates the problematic memory accesses to users.

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

FPGA-based emulation of permanent faults in ASICs can considerably improve the fault simulation time compared to traditional software-based approaches. Moreover, a hardware-based solution provides realistic behavior during fault emulation which is often required in safety-critical systems' validation. Previous emulation approaches not only suffers from considerable area (for instrumentation) and reconfiguration (for fault injection) overheads but also provides limited coverage of the target faults (and fault sites). The latter is due to difficulties in establishing a fault model equivalence when the ASIC structural netlist is passed through the design automation phases of an FPGA. This paper presents a novel approach for fast emulation of permanent faults in ASICs on state-of-the-art dynamically reconfigurable SRAM-based FPGAs while achieving fault model equivalence. Our proposed approach leverages localized run-time in-place Look Up Table (LUT) reconfigurations to avoid the time-consuming bitstream generation process for every ASIC fault. Moreover, the speed of fault injection is enhanced by direct LUT configuration data modification inside a bitstream frame. This results in 17 and 4 times improvements in fault injection speeds over vendor-provided LUT modification libraries and existing partial bitstream based approaches respectively. However, this improvement is achieved at an average 1.2 and 1.1 times degradation in area and delay metrics for the considered mapped circuits which is affordable considering the benefits in terms of the emulation speed.

Optimizing Memory Translation Emulation in Full System Emulators

The emulation speed of a full system emulator (FSE) determines its usefulness. This work quantitatively measures where time is spent in QEMU [Bellard 2005], an industrial-strength FSE. The analysis finds that memory emulation is one of the most heavily exercised emulator components. For workloads studied, 38.1% of the emulation time is spent in memory emulation on average, even though QEMU implements a software translation lookaside buffer (STLB) to accelerate dynamic address translation. Despite the amount of time spent in memory emulation, there has been no study on how to further improve its speed. This work analyzes where time is spent in memory emulation and studies the performance impact of a number of STLB optimizations. Although there are several performance optimization techniques for hardware TLBs, this work finds that the trade-offs with an STLB are quite different compared to those with hardware TLBs. As a result, not all hardware TLB performance optimization techniques are applicable to STLBs and vice versa. The evaluated STLB optimizations target STLB lookups, as well as refills, and result in an average emulator performance improvement of 24.4% over the baseline.

Characterization and compensation of network-level anomalies in mixed-signal neuromorphic modeling platforms.

Advancing the size and complexity of neural network models leads to an ever increasing demand for computational resources for their simulation. Neuromorphic devices offer a number of advantages over conventional computing architectures, such as high emulation speed or low power consumption, but this usually comes at the price of reduced configurability and precision. In this article, we investigate the consequences of several such factors that are common to neuromorphic devices, more specifically limited hardware resources, limited parameter configurability and parameter variations due to fixed-pattern noise and trial-to-trial variability. Our final aim is to provide an array of methods for coping with such inevitable distortion mechanisms. As a platform for testing our proposed strategies, we use an executable system specification (ESS) of the BrainScaleS neuromorphic system, which has been designed as a universal emulation back-end for neuroscientific modeling. We address the most essential limitations of this device in detail and study their effects on three prototypical benchmark network models within a well-defined, systematic workflow. For each network model, we start by defining quantifiable functionality measures by which we then assess the effects of typical hardware-specific distortion mechanisms, both in idealized software simulations and on the ESS. For those effects that cause unacceptable deviations from the original network dynamics, we suggest generic compensation mechanisms and demonstrate their effectiveness. Both the suggested workflow and the investigated compensation mechanisms are largely back-end independent and do not require additional hardware configurability beyond the one required to emulate the benchmark networks in the first place. We hereby provide a generic methodological environment for configurable neuromorphic devices that are targeted at emulating large-scale, functional neural networks.

Performance and power profiling for emulated Android systems

Simulation is a common approach for assisting system design and optimization. For system-wide optimization, energy and computational resources are often the two most critical issues. Monitoring the energy state of each hardware component and measuring the time spent in each state is needed for accurate energy and performance prediction. For software optimization, it is important to profile the energy and the time consumed by each software construct in a realistic operating environment with a proper workload. However, the conventional approaches of simulation often fail to produce satisfying data. First, building a cycle-accurate simulation environment for a complex system, such as an Android smartphone, is difficult and can take a long time. Second, a slow simulation can significantly alter the behavior of multithreaded, I/O-intensive applications and can affect the accuracy of profiles. Third, existing software-based profilers generally do not work on simulators, which makes it difficult for performance analysis of complicated software, for example, Java applications executed by the Dalvik VM in an Android system. To address these aforementioned problems, we proposed and prototyped a framework, called virtual performance analyzer (VPA). VPA takes advantage of an existing emulator or virtual machine monitor to reduce the complexity of building a simulator. VPA allows the user to selectively and incrementally integrate timing models and power models into the emulator with our carefully designed performance/power monitors, tracing facility, and profiling tools to evaluate and analyze the emulated system. The emulated system can perform at different levels of speed to help verify if the profile data are impacted by the emulation speed. Finally, VPA supports existing software-based profiles and enables non-intrusive tracing/profiling by minimizing the probe effect. Our experimental results show that the VPA framework allows users to quickly establish a performance/power evaluation environment and gather useful information to support system design and software optimization for Android smartphones.

An Ultra-High Speed Emulator Dedicated to Power System Dynamics Computation Based on a Mixed-Signal Hardware Platform

This paper presents an ultra-high speed hardware platform dedicated to power system dynamic (small signal) and transient (large signal) stability. It is based on an intrinsic parallel architecture which contains hybrid mixed-signal (analog and digital) circuits. For a given model, this architecture overcomes the speed of the numerical simulators by means of the so-called emulation approach. Indeed, the emulation speed does not depend on the power system size. This approach is nevertheless not competing against high-performance numerical simulators in term of accuracy and model complexity. It targets to complement the numerical simulators with the advantage of speed, portability, low cost and autonomous functioning. The proof of concept is a flexible and modular 96-node hardware platform. It is based on a reconfigurable array of power system buses called Field Programmable Power Network System (FPPNS). Details on this hardware are given. Two benchmark topologies with, respectively, 17 nodes and 57 nodes are provided. Comparisons with a digital simulator are done in terms of speed and accuracy. The calibration of the system is explained and different applications are proposed and discussed. The promising results of this hardware platform show that the design of a fully integrated solution containing hundreds of power system buses can be achieved in order to provide a low cost solution.

Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs

FPGA-based hardware emulators are often used for the verification of LSI functions. They generally have dedicated external memories, such as SDRAMs, to compensate for the lack of memory capacity in FPGAs. In such a case, access between the FPGAs and the dedicated external memory may represent a major bottleneck with respect to emulation speed since the dedicated external memory may have to emulate a large number of memory blocks. In this paper, we propose three methods, “Dynamic Clock Control (DCC),” “Memory Mapping Optimization (MMO),” and “Efficient Access Scheduling (EAS),” to avoid this bottleneck. DCC controls an emulation clock dynamically in accord with the number of memory accesses within one emulation clock cycle. EAS optimizes the ordering of memory access to the dedicated external memory, and MMO optimizes the arrangement of the dedicated external memory addresses to which respective memories will be emulated. With them, emulation speed can be made 29.0 times faster, as evaluated in actual LSI emulations.

Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

The appearance of nanometer technologies has produced a significant increase of integrated circuit sensitivity to radiation, making the occurrence of soft errors much more frequent, not only in applications working in harsh environments, like aerospace circuits, but also for applications working at the earth surface. Therefore, hardened circuits are currently demanded in many applications where fault tolerance was not a concern in the very near past. To this purpose, efficient hardness evaluation solutions are required to deal with the increasing size and complexity of modern VLSI circuits. In this paper, a very fast and cost effective solution for SEU sensitivity evaluation is presented. The proposed approach uses FPGA emulation in an autonomous manner to fully exploit the FPGA emulation speed. Three different techniques to implement it are proposed and analyzed. Experimental results show that the proposed Autonomous Emulation approach can reach execution rates higher than one million faults per second, providing a performance improvement of two orders of magnitude with respect to previous approaches. These rates give way to consider very large fault injection campaigns that were not possible in the past

Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures

Emulation of one architecture on another is useful when the architecture is under design, when software must be ported to a new platform or is being developed for systems which are still under development, or for embedded systems that insufficient resources to support the software development process. Emulation using an interpreter is typically slower than normal execution by up to 3 orders of magnitude. Our approach instead translates the program from the original architecture to another architecture while faithfully preserving its semantics at the lowest level. The emulation speeds are comparable to, and often faster than, programs running on the original architecture. Partial evaluation of architectural features is used to achieve such impressive performance, while permitting accurate statistics collection. Accuracy is at the level of the number of clock cycles spent executing each instruction (hence the description cycle-accurate ).

ATOMi: an algorithm for circuit partitioning into multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture

Logic emulation is so far the fastest method to verify the system functionality in the gate level before chip fabrication. Field-programmable gate array (FPGA)-based logic emulator with large gate capacity generally comprises a large number of FPGAs or special processors connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. This paper first describes a new interconnection architecture called TOMi (Time-multiplexed, Off-chip, Multicasting interconnection) and proposes a circuit partitioning algorithm called ATOMi (Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi. ATOMi reduces the number of off-chip signal transfers to optimize the performance for multi-FPGA system implemented by TOMi. Experimental results using Partitioning93 benchmarks show that, by adopting the proposed TOMi interconnection architecture along with ATOMi, the pin count is reduced to 14.4%-88.6% while the critical path delay is reduced to 66.1%-90.1% compared to traditional architectures including mesh, crossbar, and VirtualWire architecture.

Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture

The gate utilization of FPGAs and speed of emulation in multi-FPGA system are limited by the interconnection architecture and the number of pins. The time-multiplexing of interconnection wires is required for multi-FPGA systems incorporating several state-of-the-art FPGAs. This article proposes a circuit partitioning algorithm called SCheduling driven Algorithm for TOMi (SCATOMi) for multi-FPGA systems with interconnection architecture called Time-multiplexed, Off-chip, Multi-casting interconnection (TOMi). SCATOMi improves the performance of the TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2–81.3% while the critical path delay is reduced to 46.1–67.6% compared to traditional architectures.

Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture

The gate utilization of FPGAs and speed of emulation in multi-FPGA system are limited by the interconnection architecture and the number of pins. The time-multiplexing of interconnection wires is required for multi-FPGA systems incorporating several state-of-the-art FPGAs. This article proposes a circuit partitioning algorithm called SCheduling driven Algorithm for TOMi (SCATOMi) for multi-FPGA systems with interconnection architecture called Time-multiplexed, Off-chip, Multi-casting interconnection (TOMi). SCATOMi improves the performance of the TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2–81.3% while the critical path delay is reduced to 46.1–67.6% compared to traditional architectures.

Next generation functional test program development system

While superior-quality functional board test has been a goal for most high reliability electronics manufacturers, the time and effort for generating such test programs using today's tools and processes makes this difficult to achieve in a cost effective manner. This paper will introduce a revolutionary approach to functional board test program development that combines the comprehensiveness of software-based simulation with the speed and simplicity of hardware emulation. The result is a functional Test Program Set development system that can produce high fault coverage, diagnostic test programs in a fraction of the time it takes using traditional techniques, and at a lower unit cost. In this paper we will first provide a brief background on the strengths and weaknesses of current software and hardware TPS development techniques-simulation hot mock-up. Next, the new approach is described in detail and contrasted against the existing techniques. Finally, actual experience to date using a prototyped system is presented.

Mixing 3-V and 5-V ICs : John Williams. IEEE Spectrum, 40 (March 1993)

FPGA-based emulation of permanent faults in ASICs can considerably improve the fault simulation time compared to traditional software-based approaches. Moreover, a hardware-based solution provides realistic behavior during fault emulation which is often required in safety-critical systems' validation. Previous emulation approaches not only suffers from considerable area (for instrumentation) and reconfiguration (for fault injection) overheads but also provides limited coverage of the target faults (and fault sites). The latter is due to difficulties in establishing a fault model equivalence when the ASIC structural netlist is passed through the design automation phases of an FPGA. This paper presents a novel approach for fast emulation of permanent faults in ASICs on state-of-the-art dynamically reconfigurable SRAM-based FPGAs while achieving fault model equivalence. Our proposed approach leverages localized run-time in-place Look Up Table (LUT) reconfigurations to avoid the time-consuming bitstream generation process for every ASIC fault. Moreover, the speed of fault injection is enhanced by direct LUT configuration data modification inside a bitstream frame. This results in 17 and 4 times improvements in fault injection speeds over vendor-provided LUT modification libraries and existing partial bitstream based approaches respectively. However, this improvement is achieved at an average 1.2 and 1.1 times degradation in area and delay metrics for the considered mapped circuits which is affordable considering the benefits in terms of the emulation speed.