Abstract
The security and dependability of embedded systems are increasing due to the sensitive and condensed structure of nanodevices. As the chip area shrinks and the technologies upgrade, the probability of Single Event Upset or Multi Bit Upset proliferate which may lead to unexpected results. This article presents a fault-injection tool called EFIC-ME (Emulation based Fault Injection Control and Monitoring Enhancement) using an emulation technique with a reasonable contribution to flexibility and controllability. Existing emulation based fault-injection tools, targeting Field Programmable Gate Arrays (FPGA), reveal high efficiency and low emulation time, but they still lack the control of fault injection time. The proposed tool (EFIC-ME) achieves a low emulation time and provides a sophisticated way to inject the fault in a specific location at a specific clock cycle inside the Design Under Test (DUT). Additionally, it also employs an observability mechanism to monitor the current state of flip-flops on a user defined time. In the context of high emulation speed, it provides an Opal Kelly FPGA interface between the host controller and emulator. In order to evaluate the dependability of the proposed tool, a mechanism has been provided in terms of FoEA (Factors of emulation analysis) and fault injection rate. The FoEA estimates the failure probability of a complete DUT and the failure probability of a specific location inside the DUT which directly affects an output. The designed architecture is initially validated using simulation to verify the functional characteristics. Subsequently, the fault injection campaign has been performed on Kintex-7 FPGA for seven different DUTs. The achieved results have been discussed and compared with state-of-the-art in terms of various performance attributes.
Highlights
The high performance and low cost of embedded systems permit to satisfy the performance and efficiency characteristics of modern real-world applications
We present a fault analysis model to evaluate the dependability of either a complete Design Under Test (DUT) or a specific location inside the DUT
These 4.5% fault factor (FF) could be from different locations of the DUT which depends on the selection of test vector
Summary
The high performance and low cost of embedded systems permit to satisfy the performance and efficiency characteristics of modern real-world applications. In order to enhance the controllability of the overall process, the work in [17] presents a low cost mechanism which can inject faults in registers using a reconfigurable FPGA system It uses BRAM (Block Random Access Memory) to capture the monitored data, which needs an extra controller for read and write operations. The SEU changes an internal state of the flip-flop and it propagates into the circuit They provide a high fault rate, which increases the total power consumption and overall emulation time. In addition to an enhanced controllability, the proposed fault emulation tool advocates the use of an external FPGA named as Opal Kelly XEM 6001 [23] This FPGA provides a faster and flexible mechanism to transfer fault injection parameters from the main computer to the targeted RTL design.
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