ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs

Abstract

Fault emulation in field-programmable gate arrays (FPGAs) is a popular alternative to test the reliability of a design due to its low cost and high availability compared to traditional radiation-based approaches. Fault emulation is an instrumentation method based on inducing artificial bit flips on the design under test (DUT) to modify the content of its memory elements or the structure of the design itself. A major limitation of error emulation in FPGAs lies in the determination of the proper bits to test, which is directly related to the reliability results obtained and the execution times of the fault injection campaign. The Automatic Configuration Memory Error-injection (ACME) tool helps with this process in Xilinx FPGAs by obtaining the essential bits of an FPGA region where the DUT is. In this paper, we present ACME-2, an improved version of the tool where the translation from the FPGA region to design essential bits has been modified with architectural information of the FPGA. In this revision of the tool, redundant input/output routing bits that distort the reliability results are minimized. For the example designs used in the experiments, these modifications have led to an improvement in the precision of the reliability results as well as a reduction of the fault injection campaign runtime over the previous version of the tool.