Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-Flow Verilog HDL Designs Under the RASP-FIT Tool

Abstract

Owing to the condensed size of components in digital designs on the FPGA, it is difficult to guarantee an acceptable degree of reliability due to soft-errors. These designs are mostly available in Hardware Description Languages (HDL) at various abstraction levels, e.g. gate-level, data-flow, and behavioural. Fault Injection (FI) is a well-known technique to assess the dependability of such designs. Broadly, FI techniques for FPGA-based designs are categorized into emulation and simulation-based techniques. Simulation-Based FI (SBFI) tools work on hardware models of designs and help designers to test and verify designs at an early phase of the FPGA design & development flow. Testing, dependability analysis, and fault simulation applications require a faulty model of the original design during fault injection campaign. Therefore, we require a tool which can automatically generate the faulty model of the original design written at any abstraction levels and perform fault injection testing and dependability analysis. In this paper, a fault injection tool (RASP-FIT) is presented, which consists of an automatic code modifier (fault injection algorithm), fault injection control unit and result analyser. Previously, the tool is used for code-modification, test and hardness analysis for gate-level designs. In this paper, an enhancement of a code modifier along with result analyser techniques are applied to the data-flow benchmark designs and presented.