Emitter Region Research Articles

Bipolar transistor with quantum well base

We report in this study the modeling of a heterostructure bipolar transistor (HBT) where the base is designed as a quantum well. The transistor structure consists of a base layer of GaAs that is heavily p-type doped. The 0.024μm base is sandwiched between wide band gap InxGa1−xP which composes the n-type emitter and collector layers immediately adjacent to the base. The thickness of the base was chosen so that it is comparable to the wavelength of the electrons passing though it. There are two heavily doped cap layers of InGaAs at the emitter contact. The remainder of the emitter and collector regions are composed of GaAs. The purpose of this design is to filter the energies and velocities of electrons as they pass through the base region that forms a quantum barrier to electrons and a quantum well to holes. This should result in a significant decrease of noise in comparison to that observed in non-quantum base HBTs. As expected, the thin quantum well improves the collection of injected carriers, which in turn boosts the DC gain (β) to 750 and increases the power of the novel transistor by a factor of six, in comparison to a commercially available HBT with a similar non-quantum well structure. At high frequencies, the gain of the device is increased by about 5dB over the non-quantum base HBT that this device is based upon. Additionally, the cutoff frequency is improved from 20 to 50GHz. Modeling of the novel transistor was done using Silvaco ATLAS™. This study will continue with the fabrication of experimental wafers.

Determination of front surface recombination velocity of silicon solar cells using the short-wavelength spectral response

A method of determination of recombination velocity S f of minority carriers at the front surface of an n +–p–p +(p +–n–n +) silicon solar cell in which the n +(p +) front emitter is made by diffusion of dopant impurity in the p(n) region is presented. This method uses the short-wavelength spectral response of the cell to determine S f and is applicable if the front emitter of the cell has a linearly varying built-in field. It was applied to a p +–n–n + solar cell that had a Gaussian distribution of the dopant impurity in the p + front emitter up to a depth of 0.078 μm from the surface. Using the spectral response data of cell in 380 nm< λ< 500 nm range S f was found to have a nearly constant value ∼6×10 5 cm s −1 in 400 nm< λ<460 nm range. Below and above this wavelength range the value of S f was found to be slightly smaller. For comparison the value of S f was also determined assuming the p + region to be uniformly doped, and this value was found to be significantly smaller than based on the diffused emitter model. The analysis showed that for a diffused junction cell, the assumption that the front emitter is uniformly doped, ignores the presence of the built-in field in the emitter region and leads to overestimation of minority carrier recombination in the emitter. Consequently for a given contribution of the front emitter region to the spectral response of the cell, this assumption underestimates the front surface recombination and determines a smaller value of S f. On the other hand, the present method can be expected to determine a realistic value of S f independent of λ for most diffused junction silicon solar cells using the spectral response data in a suitable short-wavelength range since each such cell indeed has a built-in electric field in the emitter region.

Thermal Model of the Hollow Cathode Using Numerically Simulated Plasma Fluxes

The first results from a hollow cathode thermal model are presented. The thermal model uses the spatially distributed plasma fluxes, calculated by a two-dimensional axisymmetric model of the plasma inside the emitter region, as the heat source to predict the hollow cathode and insert temperatures. The computed insert temperature profiles are compared with measured values for a cathode similar to the 0.635-cm diameter discharge cathode used in the NASA solar electric propulsion technology applications readiness ion engine. The insert temperatures can be used to predict cathode life from barium depletion. The present results and related experimental studies yield three important conclusions. First, the emitter in the NASA solar electric propulsion technology applications readiness hollow cathode does not operate in the emission-limited regime. The thermionic electron current is about 20 A higher than the discharge current and requires significant reverse electron flux from the plasma to satisfy current continuity. Second, the high-plasma density near the centerline of the cathode results in power deposition on the orifice plate that is more than twice the emitter power deposition. Third, despite a higher heat load to the orifice plate, the operating temperature where it would be measured by a thermocouple is approximately 100°C lower than the emitter. The lower orifice plate temperature is due to poor thermal contact between the emitter and the cathode tube and higher than anticipated radiative losses from the external surface of the heater.

All injection level power PiN diode model including temperature dependence

A novel power PiN diode model is derived based on the generalised all-injection level minority carrier drift–diffusion theory. An equivalent lossy transmission lines describing the carriers transport trough arbitrarily doped emitter and base quasi-neutral regions are defined. The extended electro-thermal diode model including temperature dependences of carrier transport parameters is also described and implemented in circuit simulator PSPICE. By tuning a small set of model parameters, an excellent agreement of modelling results with numerical simulations of realistic power PiN diode is obtained for different switching conditions and temperatures.

Characterization and modeling of InGaAs/InAsP thermophotovoltaic converters under high illumination intensities

Thermophotovoltaic converters based on In0.69Ga0.31As/InAs0.34P0.66 have been fabricated, characterized experimentally, and modeled. Good device performance has been achieved with an open-circuit voltage of 1.46 V, short-circuit current density of 1.06 A/cm2, and a fill factor of 71.3% for a four-junction cell under an optical power density of 3.4 W/cm2. Key material parameters have been extracted from measured device characteristics, providing a detailed quantitative understanding of the dependence of device performance on the electro-optical properties of the InGaAs/InAsP material system. Extracted minority carrier lifetimes of 106 ns in the p-type base and 0.3 ns in the n-type emitter regions were obtained, limited by radiative and Auger recombination, respectively. The recombination velocity for the InGaAs/InAsP interface is found to be below 2000 cm/s. The parameter analysis provides guidance for the design of a high-efficiency monolithically integrated module for use under high illumination intensities.

The growth kinetics and optical confinement studies of porous Si for application in terrestrial Si solar cells as antireflection coating

The mesoporous porous-silicon (PS) layers were grown on 〈1 0 0〉, 〈1 1 0〉, and 〈1 1 1〉 oriented wafers at constant current density of 20 mA cm −2. The pore sizes and surface morphologies were measured by atomic force and scanning electron microscopes. The thickness x of the PS formed and the refractive index were measured by an ellipsometer as a function of time duration t (in min) of anodization. The x vs. t data were fitted into a power law x= at c where c is a dimensionless constant and growth kinetics was established. The growth is practically independent of orientation. This is due the reason that the growth rate is controlled largely by the availability of holes which exchange their charge with oxidizing species and desirably large concentrations of holes were available at current density of 20 mA cm −2. For a similar reason the growth of PS layer on the front surface of the n + region of n +–p solar cells could also be done at current density of ∼20 mA cm −2 nearly at the same rate. A large concentration of holes could be injected from p region into the n + region because the positive contact was made on the p side and thus the junction was forward biased. The PS ARC of thickness 70 nm showed increase ∼26% in the short circuit current density J sc and 24% in efficiency of the cells. However, the improvement in the values of the open circuit voltage V oc were lower than the expected value indicating that the PS layers had enhanced recombination of minority carriers at the front surface or in the front emitter region immediately below the PS layer.

Localisation of the p-n junction in poly-silicon thin-film diodes on glass by high-resolution cross-sectional electron-beam induced current imaging

High-resolution scanning electron microscope, focused ion beam (FIB) microscope, and electron-beam induced current (EBIC) images are taken on large-grained polycrystalline silicon thin-film diodes on glass. To aid understanding of the plan-view EBIC images obtained, trenches are cut into the diodes in the FIB microscope, and the p-n junction then located and examined in the diode's cross section using high-resolution EBIC. Diffusion of aluminium atoms from the heavily doped emitter region into the base region of the diode along grain boundaries during material fabrication is found to have locally altered the junction's location and therefore alters the EBIC signal in these regions. Using this method allows a fast and easy location of the p-n junction in these diodes, in addition to aiding in the identification of unusual junction deviations which complicate the interpretation of plan-view EBIC images.

Self-Aligned SiGe HBT Based on Combined Dry and Wet Etching

In this paper, a self-aligned SiGe/Si HBT has been fabricated based on dry/wet etching, where Si and SiGe materials were etched by KOH (potassium hydroxide) solution and SF6(sulfur hexafluoride). It is a key technology to control the etch of ultra-thin Si and SiGe film. When N+/N silicon in emitter region is etched, the length of etch time is critical. Despite a small lateral etch, dry etching doesn't benefit the realization of self-alignment process, nor benefit improvement of yield and fmax. In this paper, based on the chemical properties of silicon and germanium, dry and wet etches were properly combined to etch silicon and silicon germanium. First, N+/N Si outside emitter was etched with intentional lateral etch using KOH solution. Then, SiGe was etched by SF6. Finally, SiGe HBT with self-alignment of emitter to base has been developed. The measured results are: cutoff frequency fT=103GHz, maximum oscillation frequency fmax=124GHz.

Characterization of Ge-on-Si virtual substrates and single junction GaAs solar cells

A virtual substrate consisting of a Ge layer grown directly on Si without an intervening SiGe graded layer is characterized. The nominally 100% Ge overlayer is fully relaxed and contains a small amount (3%) of unintentional Si. A dislocation density of 108 cm−2 is estimated for the virtual substrate prior to GaAs epitaxial growth, which is reduced by a factor of 100 after the growth of GaAs. On this novel virtual substrate 1 cm2 single-junction GaAs photovoltaic cells were realized with an efficiency of 11.7% under AM0 compared with 20.2% for cells grown on a crystalline Ge substrate. Due to the high dislocation density a 50-fold higher dark current is measured in the virtual substrate cells compared to the crystalline Ge cells, leading to a lower short circuit current and open-circuit voltage of the cells fabricated on the virtual substrates. The post-GaAs growth dislocation density is estimated as 1 × 107 cm−2 in the base region and 4 × 105 cm−2 in the emitter region based on modelling and measurements.

Application of junction capacitance measurements to the characterization of solar cells

The quasi-static capacitance-voltage ( C-V) technique measures the dependence of junction capacitance on the bias voltage by applying a slow, reverse-bias voltage ramp to the solar cell in the dark, using simple circuitry. The resulting C-V curves contain information on the junction area and base dopant concentration, as well as their built-in potential. However, in the case of solar cells made on low to medium resistivity substrates and having thick emitters, the emitter dopant profile has to be taken into account. A simple method can then be used to model the complete C-V curves, which, if the base doping is known, permits one to estimate the emitter doping profile. To illustrate the method experimentally, several silicon solar cells with different base resistivities have been measured. They comprise a wide range of areas, surface faceting conditions and emitter doping profiles. The analysis of the quasi-static capacitance characteristics of the flat surface cells resulted in good agreement with independent data for the wafer resistivity and the emitter doping profile. The capacitance in the case of textured surfaces is a function of the effective junction area, which is otherwise difficult to measure, and is essential to understand the emitter and space charge region recombination currents. The results indicate that the effective area of the junction is not as large as the area of the textured surface.

Influence of the minority carrier extracted by the base electrode on current gain of bipolar power transistors

Bipolar power transistors (BPTs) are widely used in various kinds of high-voltage and medium-power applications due to their low on-state voltage drop and high current capability. In this paper, the influence of minority carrier extracted by the base electrode on the current gain of BPTs is presented first and studied in detail. It is suggested that the minority carrier extracted by the base electrode is responsible for the current gain change. Based upon this theory, a structure with a local heavily-doped base (LHDB) to increase the current gain is proposed and investigated. The increase of the current gain can be controlled by the doping of the LHDB and the location of the LHDB relative to the emitter region. The analytical results show a good agreement with the numerical simulation and experiment results.

Photoresponse of gated p-silicon field emitter array and correlation with theoretical models

Improved fabrication and conditioning techniques for gated p-Si field emitter arrays (FEAs) (1×1mm2 in size with 50×50 emitters) greatly reduces the bulk damage and surface states. Consequently, only 0.9μA of the anode dark field-emission current was measured for 50V applied gate potential with a very low gate leakage current. At these low gate leakage currents, the transition between the tunneling-limited field-emission regime and the supply-limited saturation regime is clearly revealed in current-voltage plots. This transition is accompanied by a reduction in the anode current fluctuation. The standard deviation of the noise current drops from a few percent in the tunneling-limited regime to &amp;lt;1% in the supply limited regime at 50V. A photocurrent of 0.41mA was obtained for photoexcitation at 840nm wavelength. This corresponded to 40dB contrast ratio between the photocurrent and the dark current at room temperature. Additionally, our findings showed that surface states were fully depleted at low applied fields, the concentration of bulk defects was low and the area contributing to the dark current was confined to the emitter regions. In contrast, previously reported ungated Si field emitters had high concentrations of surface states and bulk defects. Furthermore, the contributing area to the dark current corresponded to the whole area of the device as opposed to only the emitter areas for a gated FEA. Photofield emission and dark current measurements from our gated p-Si FEA correlate well to theoretical models without requiring cooling to liquid-nitrogen temperatures.

Device Simulation and Design Optimization for Diamond Based Insulated-gate Bipolar Transistors

ABSTRACTA diamond based insulated gate bipolar transistor is incorporated into a two-dimensional device simulator (MEDICI) to examine the current gain (β) and potential distribution across the device. Initially, work has focused on an important component of IGBT structure, the PNP bipolar transistor, which has been simulated and is reported upon in this paper. Empirical parameters for emitter and collector regions were used. Various carrier concentrations for base region were used to optimize the simulation. It was found that decreasing the thickness of base region leads to an increase in current gain. A buffer layer is needed to prevent the punch-through at low carrier concentration in the base region. Various approaches of increasing the current gain are also discussed in this paper.

Hollow cathode theory and experiment. II. A two-dimensional theoretical model of the emitter region

Despite their long history and wide range of applicability that includes electric propulsion, detailed understanding of the driving physics inside orificed hollow cathodes remains elusive. The theoretical complexity associated with the multicomponent fluid inside the cathode, and the difficulty of accessing empirically this region, have limited our ability to design cathodes that perform better and last longer. A two-dimensional axisymmetric theoretical model of the multispecies fluid inside an orificed hollow cathode is presented. The level of detail attained by the model is allowed by its extended system of governing equations not solved for in the past within the hollow cathode. Such detail is motivated in part by the need to quantify the effect(s) of the plasma on the emitter life, and by the need to build the foundation for future modeling that will assess erosion of the keeper plate. Results from numerical simulations of a 1.2-cm-diam cathode operating at a discharge current of 25A and a gas flow rate of 5SCCM show that approximately 10A of electron current, and 3.45A of ion current return back to the emitter surface. The total emitted electron current is 33.8A and the peak emitter temperature is found to be 1440K. Comparisons with the measurements suggest that anomalous heating of the plasma is possible near the orifice region. The model predicts heavy species temperatures as high as 2034K and peak voltage drops near the emitting surface not exceeding 8V.

A New Emitter Switched Thyristor (EST) employing Trench Segmented p-base

A new emitter switched thyristor (EST) employing trench segmented p-base, which successfully improves the forward I–V and switching characteristics with decreasing the device active area, is proposed and verified experimentally with using shallow trench process of novel junction termination extension (JTE) method. The latching current of EST is determined by the p-base resistance of upper npn transistor. Floating n+emitter of conventional EST is enlarged to obtain large base resistance. However, the proposed EST increases the p-base resistance with shorter floating n+ emitter than that of conventional one. Shallow trench in floating emitter region forms the highly resistive p-base region under the bottom of trench. The experimental results show that the shortened floating n+ emitter and lowered latching current of proposed EST decrease experimentally the forward voltage drop by 17.7% and snap-back phenomenon with small active area. The breakdown voltage of series lateral MOSFET of proposed EST is increased from 7 to 14V due to the trench filled with oxide which results in vertical redistribution of electric field, therefore current saturation capability and forward biased safe operating area (FBSOA) of proposed EST are enhanced. The simulation results show that the switching operation is performed successfully at the blocking voltage of 600V and Eoff of the proposed one is reduced by 3.7%. The measured inductive load switching characteristics also shows that Eoff of proposed one is improved by 7.2%.

Understanding the Formation and Temperature Dependence of Thick-Film Ag Contacts on High-Sheet-Resistance Si Emitters for Solar Cells

Physical and electrical properties of screen-printed Ag thick-film contacts were studied and correlated to understand and achieve good-quality ohmic contacts to high-sheet-resistance emitters for solar cells. Analytical microscopy and surface analysis techniques were used to study the Ag–Si contact interface of three different screen-printed Ag pastes (A, B, and PV168) subjected to high and conventional temperature firing conditions. At firing, all three pastes failed on a emitter because of incomplete etching of the silicon nitride film (PV168), an irregular small distribution of regrown Ag crystallites (paste A), or an excessive diffusion of Ag into the p-n junction (paste B). At a firing temperature of , paste A gave a lower open-circuit voltage because of the diffusion of Al from the glass frit into the emitter region. Paste B failed because of the formation of very large Ag crystallites that shunted the p-n junction. Of the three pastes, the PV168 paste from DuPont gave the best contact quality on a emitter with a solar cell fill factor of 0.782 only after annealing in a hydrogen atmosphere.

High-Performance InGaP/GaAs HBTs With Compositionally Graded Bases Grown by Solid-Source MBE

N-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with compositionally graded In/sub x/Ga/sub 1-x/As (Be doped) bases have been successfully grown by solid-source molecular beam Epitaxy (SSMBE) using a gallium phosphide (GaP) decomposition source. In this paper, the dc and RF characteristics of HBTs with different indium mole fractions in the graded In/sub x/Ga/sub 1-x/As base (x:0 /spl rarr/ ;0.1 and x:0 /spl rarr/ 0.05) are measured to investigate optimum-grading profiles. The measured average current gains, /spl beta/s of a control sample, a 10% graded-base sample and a 5% graded-base sample, are 162, 397 and 362, respectively. To our knowledge, these current gains are the highest values ever reported in compositionally graded-base InGaP/GaAs HBTs with a base sheet resistance R/sub sh/ of /spl sim/200 /spl Omega//sq establishing a new benchmark for InGaP/GaAs HBTs. Furthermore, these compositionally graded-base HBTs show higher unity current/gain cutoff frequency, f/sub T/ and maximum oscillation frequency, f/sub max/. Compared to the control sample with the same base thickness, the base transit time /spl tau//sub B/ of the graded sample is reduced by /spl sim/15% to /spl sim/20% by the induced built-in potential, resulting in an increase of f/sub max/ from 16 to 18.5 GHz in a device with an emitter size of 10/spl times/10 /spl mu/m/sup 2/. Additionally, for the 5% graded-base sample, with a 5/spl times/5 /spl mu/m/sup 2/ emitter region, f/sub T/ and f/sub max/ are 16.3 and 33.8 GHz, respectively, under low-level collector current. These results demonstrate that InGaP/GaAs HBTs with In/sub x/Ga/sub 1-x/As graded-base layers (x:0 /spl rarr/ 0.05) have the potential for high-speed analogue to digital converters.

Lateral High-Speed Bipolar Transistors on SOI for RF SoC Applications

This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental f/sub T//f/sub max/ of the high-speed device are 17/28 GHz, the second fastest reported f/sub T/ for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured f/sub T//f/sub max/ of 12/30 GHz and BV/sub CEO/ of over 25 V produces a Johnsons product well above 300 GHz /spl middot/V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.

Photoreflectance characterization of InP∕GaAsSb double-heterojunction bipolar transistor epitaxial wafers

We report photoreflectance (PR) measurements of InP∕GaAsSb double-heterojunction bipolar transistor epitaxial wafers grown by metalorganic vapor-phase epitaxy and discuss the correlation between the spectra and the electrical characteristics of the emitter–base (E∕B) heterojunctions. The origin of Franz–Keldysh oscillations (FKOs) in the PR spectra was identified by step etching of the samples. The current–voltage characteristics of the E∕B heterojunctions were examined by fabricating devices. FKOs from both the emitter and collector regions were observed in the wafers where the recombination forward current at the E∕B heterojunction was suppressed. In contrast, when the recombination current was significant, no emitter-related FKOs were observed. The absence of the FKOs from the emitter indicates the high concentration of recombination centers at the E∕B heterojunction.

Non‐destructive, room temperature characterization of wafer‐sized III–V semiconductor device structures using contactless electromodulation and wavelength‐modulated surface photovoltage spectroscopy

AbstractWe review the use of the contactless methods of photoreflectance (PR), contactless electroreflectance (CER) and wavelength modulated differential surface photovoltage spectroscopy (DSPS) for the nondestructive, room temperature characterization of a wide variety of wafer‐scale III–V semiconductor device structures. Some systems that will be discussed include heterojunction bipolar transistors (including the determination of the built‐in fields/doping levels in the emitter and collector regions, alloy composition, and dc current gain factor), pseudomorphic GaAlAs/InGaAs/GaAs high electron mobility transistors (including the determination of the composition, width, and two‐dimensional electron gas density in the channel), InGaAsP/InP quantum well edge emitting lasers (including the detection of p‐dopant interdiffusion), vertical‐cavity surface‐emitting lasers (determination of fundamental conduction to heavy‐hole excitonic transition and cavity mode). (© 2005 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)