Emitter Layout Research Articles

Chip-scale blue light phased array.

Compact beam steering in the visible spectral range is required for a wide range of emerging applications, such as augmented and virtual reality displays, optical traps for quantum information processing, biological sensing, and stimulation. Optical phased arrays (OPAs) can shape and steer light to enable these applications with no moving parts on a compact chip. However, OPA demonstrations have been mainly limited to the near-infrared spectral range due to the fabrication and material challenges imposed by the shorter wavelengths. Here, we demonstrate the first chip-scale phased array operating at blue wavelengths (488 nm) using a high-confinement silicon nitride platform. We use a sparse aperiodic emitter layout to mitigate fabrication constraints at this short wavelength and achieve wide-angle beam steering over a 50° field of view with a full width at half-maximum beam size of 0.17°. Large-scale integration of this platform paves the way for fully reconfigurable chip-scale three-dimensional volumetric light projection across the entire visible range.

Influence of Scaling and Emitter Layout on the Thermal Behavior of Toward-THz SiGe:C HBTs

An extensive on-wafer experimental campaign is carried out to determine the thermal resistance dependence on scaling and emitter geometry in state-of-the-art toward-THz silicon–germanium bipolar transistors designed and fabricated within the framework of the European DOTFIVE project. The extraction is performed through a robust procedure which—differently from classic approaches—exploits an accurately calibrated thermometer relating base-emitter voltage to junction temperature. Experimental data are then used to assess the accuracy of scalable thermal resistance laws for advanced transistor models; it was found that at least four parameters are needed to ensure a favorable agreement over wide ranges of emitter widths and lengths.

Scaling influence on the thermal behavior of toward-THz SiGe:C HBTs

An extensive on-wafer experimental campaign is performed to extract the thermal resistance of state-of-the-art toward-THz silicon germanium bipolar transistors designed and developed within the European DOTFIVE project. The dependence of this critical parameter on scaling, as well as on the emitter layout, is carefully evaluated, and the resulting junction temperatures are determined.

Improved SiGe power HBT characteristics by emitter layout

A new emitter finger layout in SiGe HBT to reduce thermal-coupling is presented in this study. By redistributing the emitter fingers of various SiGe HBTs, the thermal resistance reduces significantly from 133 to 88K/W under room temperature. Thus, in dc performance, output conductance increases from −2.0 to −1.6mA/V. In ac performance, the fMAX shows an improvement over 10%. In power performance, the linear power gain, P1dB and PAEatP1dB increase by 0.5dB, 1.5dB and 6.2% at 1.8GHz, respectively.