Emerging Memory Devices Research Articles

(Invited) Novel Neuromorphic Computing Paradigms Enabled By Emerging Memory Devices

Implementation of Artificial Intelligence and Machine Learning algorithms on conventional Von Neumann computing architectures are crippled by the memory-wall bottleneck. To overcome these issues, novel computing architectures with high-bandwidth memories, in-memory computing, and near-memory computing capabilities are being developed. Almost all of these architectures will benefit from high-density on-chip non-volatile memories, offered by the emerging non-volatile memory devices. Additionally, emerging memory devices offer rich device physics that can be leveraged for the implementation of novel computing paradigms. This paper will talk about three such emerging memory technologies: Vertical-Thin Film Transistors-Resistive Random Access Memory (V-TFT-RRAMs), Gated-RRAMs, and Ferroelectric Field Effect transistors (FeFETs). A comparative studies of various conventional neuromorphic computing approaches that can be implemented using these devices will be discussed. Finally, materials and device requirements and pending challenges will be discussed by successful realization of the proposed computing approaches. Implementation of Artificial Intelligence and Machine Learning algorithms on conventional Von-Neumann computing architectures are crippled by the memory-wall bottleneck. To overcome these issues, novel computing architectures with high-bandwidth memories, in-memory computing, and near-memory computing capabilities are getting developed. Almost all of these architectures will benefit from high-density on-chip non-volatile memories, offered by the emerging non-volatile memory devices. Additionally, emerging memory devices offer a rich set of device physics that can be leveraged for the implementation of novel computing paradigms. This paper will talk about three such emerging memory technologies: Vertical-Thin Film Transistors-Resistive Random Access Memory (V-TFT-RRAMs), Gated-RRAMs, and Ferroelectric Field Effect Transistors (FeFETs). A comparative studies of various unconventional and brain-inspired neuromorphic computing approaches that can be implemented using these devices will be discussed. Finally, materials and device requirements and pending challenges will be discussed for these device technologies.

(Invited) Thermodynamics of Oxygen Transport in Resistive and Electrochemical Memory

Many neuromorphic computing architectures contain emerging memory devices that function through oxygen migration. Examples include resistive memory1 (ReRAM) and electrochemical memory2 (ECRAM), where tuning the distribution of oxygen vacancies enables analog information states. In this presentation, we discuss how oxygen transport in many metal oxides do not obey the drift-diffusion equation, which assumes ideal solution thermodynamics. Instead, the metal oxides undergo composition phase separation into oxygen-rich and oxygen-poor phases. This phase separation explains the long information retention time of ReRAM3. We further use this phase separation to improve the information retention time of oxygen-based ECRAM4,5 by at least ten orders of magnitude, yielding the highest temperature analog nonvolatile memory.

(Invited) An Interplay between Electronic and Ionic Processes in Oxide Resistive Switching Devices

Emerging memory devices play a major role in implementing artificial neural networks as basic types of neuromorphic hardware. They provide extra functionality to conventional CMOS technology, such as the ability to implement non-volatile memory within a nanoscale region on the chip. Among 2-terminal devices, the resistive switching random access memory (RRAM) devices are very promising for these applications. However, the mechanisms of resistance changes depend on the oxide and metal electrode material and are still debated. Under an applied stress bias, MIM devices experience changes in their resistance from relatively large, in the high resistance state (HRS), to relatively low, in the low resistance state (LRS). These effects have generally been attributed to defect generation and aggregation in the oxide and depend on the chemical nature of metal electrodes. Using multiscale modelling, we investigate the role of electron injection and hydrogen incorporation inside amorphous (a) oxide films of SiO2, HfO2, Al2O3 and at interfaces with Si and TiN electrodes in creation of new defects, oxide degradation, and resistance change. The initial models of a-SiO2, a-HfO2 and a-Al2O3 structures are created using classical force-fields and the LAMMPS package. The volume and geometry of all structures are fully optimized using density functional theory (DFT) implemented in the CP2K code with the range-separated hybrid PBE0-TC-LRC functional, as described in detail in [1]. The results demonstrate that hole injection into amorphous SiO2, HfO2 and Al2O3 leads to hole localization at low-coordinated O sites in the amorphous network [2]. Injected extra electrons localize in amorphous SiO2 and HfO2 in deep states about 3.0 eV below the mobility edge [2]. Trapping of up to two electrons at intrinsic sites results in weakening of Si-O and Hf-O bonds and emergence of efficient bond breaking pathways for producing neutral O vacancies and interstitial Oi 2- ions with low activation barriers [2]. These barriers as well as barriers for migration of the O2- ion (< 0.5 eV) are further reduced by bias application. Simulations of SiO2/TiN interfaces [3] explain how, as a result of electroforming, the system undergoes very significant structural changes with the oxide being significantly reduced, interface being oxidized, and part of the oxygen leaving the system. Creation of O vacancies facilitates trap-assisted tunnelling through oxide films and is responsible for oxide charging and leakage current. Hydrogen and metal incorporation from metal electrodes leads to creation of additional defects in the oxide. DFT calculations of the incorporation and diffusion of Ag in Ag/SiO2/Me (Me=W or Pt) RRAM devices [4] show how the interplay between Ag+ ion diffusion, electron injection and vacancy creation lead to the formation of Ag clusters and filaments. Atomistic simulations of defect creation in amorphous oxide films are combined with kinetic simulations of trap assisted tunnelling of electrons and ionic diffusion through oxide [5,6]. They provide the mechanisms and time evolution of oxide charging and degradation. These mechanisms are used to simulate the kinetics of dielectric breakdown in devices and explain the mechanisms of set and reset in RRAM devices.[1] A-M. El-Sayed et al., Phys, Rev. B89, 125201 (2014)[2] J. Strand et al., J. Phys.: Condens. Matter30,233001 (2018)[3] J. Cottom et al. ACS Appl. Mater. Interfaces 11, 36232 (2019)[4] K. Patel et al. Microel. Reliab. 98, 144 (2019)[5] A. Padovani et al., J. Appl. Phys. 121, 155101 (2017)[6] J. Strand et al. J. Appl. Phys. 131, 234501 (2022)

Understanding and Characterizing Side Channels Exploiting Phase-Change Memories

Recent advances in non-volatile memory (NVM), together with their performance-optimized architectural schemes, position NVMs as promising building blocks for future main memory. However, the security of such techniques has not been explored. This article performs the first study on information leakage threats in phase change memories (PCM). We propose an attack framework, R-SAW, that systematically investigates side channel vulnerabilities in representative read techniques under inter-line and intra-line interleaving for multi-level cells. Our evaluation shows that the new side channels can accurately leak program secrets (e.g., crypto keys) and are extremely robust to noise. Our work highlights the need to understand microarchitecture security for emerging memory devices.

Chromatic Plasmonic Polarizer-Based Synapse for All-Optical Convolutional Neural Network.

Emerging memory devices have been demonstrated as artificial synapses for neural networks. However, the process of rewriting these synapses is often inefficient, in terms of hardware and energy usage. Herein, we present a novel surface plasmon resonance polarizer-based all-optical synapse for realizing convolutional filters and optical convolutional neural networks. The synaptic device comprises nanoscale crossed gold arrays with varying vertical and horizontal arms that respond strongly to the incident light's polarization angle. The presented synapse in an optical convolutional neural network achieved excellent performance in four different convolutional results for classifying the Modified National Institute of Standards and Technology (MNIST) handwritten digit data set. After training on 1,000 images, the network achieved a classification accuracy of over 98% when tested on a separate set of 10,000 images. This presents a promising approach for designing artificial neural networks with efficient hardware and energy consumption, low cost, and scalable fabrication.

Materials and challenges of 3D printing of emerging memory devices

The continuous development of the semiconductor industry to meet the increasing demand of modern electronic devices which can enhance computing capabilities is attributed to the exploration of efficient, simple, high-speed operation and multistate information storage capacity of electronic devices called memory devices. Nowadays, one of the main challenges the industry faces is limitations in manufacturing as the current fabrication pathway is complex and relies on the use of rigid substrates that do not match with the needs of industry for flexible, bendable electronics. 3D printing has a huge potential to address this challenge and to completely replace the current fabrication pathways and protocols. In this paper, the materials and the 3D printing technologies that have been explored to fabricate an emerging flexible, bendable memory device will be presented.

Unveiled Ferroelectricity in Well‐Known Non‐Ferroelectric Materials and Their Semiconductor Applications

AbstractFerroelectric materials are considered ideal for emerging memory devices owing to their characteristic remanent polarization, which can be switched by applying a sufficient electric field. However, even several decades after the initial conceptualization of ferroelectric memory, its applications are limited to a niche market. The slow advancement of ferroelectric memories can be attributed to several extant issues, such as the absence of ferroelectric materials with complementary metal–oxide–semiconductor (CMOS) compatibility and scalability. Since the 2010s, ferroelectric memories have attracted increasing interest because of newly discovered ferroelectricity in well‐established CMOS‐compatible materials, which are previously known to be non‐ferroelectric, such as fluorite‐structured (Hf,Zr)O2 and wurtzite‐structured (Al,Sc)N. With advancing material fabrication technologies, for example, accurate chemical doping and atomic‐level thickness control, a metastable polar phase, and switchable polarization with a reasonable electric field can be induced in (Hf,Zr)O2 and (Al,Sc)N. Nonetheless, various issues still exist that urgently require solutions to facilitate the use of the ferroelectric (Hf,Zr)O2 and (Al,Sc)N in emerging memory devices. Thus, ferroelectric (Hf,Zr)O2 and (Al,Sc)N are comprehensively reviewed herein, including their fundamental science and practical applications.

Effect of Al Concentration on Ferroelectric Properties in HfAlOx‐Based Ferroelectric Tunnel Junction Devices for Neuroinspired Applications

Since HfOx‐based ferroelectric tunnel junctions (FTJs) are attractive compared to perovskite‐based FTJs and other emerging memory devices, they are being actively studied recently. They have advantages such as a simple metal–insulator–metal structure, complementary metal oxide semiconductor (CMOS) compatibility, non‐destructive operation, and low power consumption. Moreover, doped HfOx‐based FTJs are in the spotlight in terms of neuromorphic engineering as a way of advancing from the von Neumann structure. In particular, Al dopant is effective for inducing ferroelectric properties due to its smaller radius than that of Hf. The optimal concentration of Al varies depending on the device materials and the annealing conditions during deposition. Therefore, in‐depth research is required for neuromorphic applications. Herein, the properties of FTJ devices according to Al doping concentrations are analyzed. Subsequently, using the device with the highest remanent polarization, neuromorphic applications are implemented, including spike‐timing‐dependent plasticity (STDP), paired‐pulse facilitation (PPF), long‐term potentiation, and depression. The characteristics in different frequency regions are also studied to satisfy the demand for fast switching. Finally, the FTJ device is used as a physical reservoir in reservoir computing for efficient processing of time‐dependent inputs.

Recent Progress of the Cation Based Conductive Bridge Random Access Memory

Demand for new computing systems equipped with ultra-high-density memory storage and new computer architecture is rapidly increasing with the tremendous increment of the amount of data produced and/or reproduced. In particular, the requirement for technology development is growing as conventional storage devices face the physical limitations for scaling down and the data bottleneck that the Von Neumann architecture increases. Among the recent emerging memory devices, the conductive bridge random access memory (CBRAM) has superior switching properties and excellent scalability to be adopted as the next-generation storage device and as the hardware implementation of the neuromorphic computing system. In this review, the previous papers on the resistive switching mechanism of CBRAM and the precedent CBRAM devices exploiting various materials proposed by many research groups are introduced. The principle of CBRAM is discussed including the operation mechanism, switching materials, and the challenges that need to be solved. A wide selection of materials including metal oxides, Chalcogenides, and other non-oxides have been examined as the electrolyte layer of the CBRAM. Various switching materials, device engineering, and material innovation approaches were introduced, and the research results for solving the problems of CBRAM were reviewed in depth.

Emerging Memory Devices Beyond Conventional Data Storage: Paving the Path for Energy-Efficient Brain-Inspired Computing

The current state of neuromorphic computing broadly encompasses domain-specific computing architectures designed to accelerate machine learning (ML) and artificial intelligence (AI) algorithms. As is well known, AI/ML algorithms are limited by memory bandwidth. Novel computing architectures are necessary to overcome this limitation. There are several options that are currently under investigation using both mature and emerging memory technologies. For example, mature memory technologies such as high-bandwidth memories (HBMs) are integrated with logic units on the same die to bring memory closer to the computing units. There are also research efforts where in-memory computing architectures have been implemented using DRAMs or flash memory technologies. However, DRAMs suffer from scaling limitations, while flash memory devices suffer from endurance issues. Additionally, in spite of this significant progress, the massive energy consumption needed in neuromorphic processors while meeting the required training and inferencing performance for AI/ML algorithms for future applications needs to be addressed. On the AI/ML algorithm side, there are several pending issues such as life-long learning, explainability, context-based decision making, multimodal association of data, adaptation to address personalized responses, and resiliency. These unresolved challenges in AI/ML have led researchers to explore brain-inspired computing architectures and paradigms.

Device Modeling Bias in ReRAM-Based Neural Network Simulations

Emerging technologies based on resistive switching (ReRAM) devices promise to improve the speed and energy efficiency of next generation machine learning accelerators, but further research is required for achieving commercial maturity. System-level prototyping with emerging devices is costly, and algorithmic investigations require hardware neural network modeling which often deviates from experimental reality. In this work, the concept of modeling bias is proposed as a way to quantify this deviation and support reliable evaluation of device populations in the context of neural network algorithms. While applicable to other device modeling techniques, modeling bias is investigated here using jump tables - a promising physics-less technique to model emerging memory devices for hardware networks. Questions about the fidelity of these tables in relation to stochastic device behavior are answered. Two methods of jump table modeling – binning and a novel Optuna-optimized binning - are explored using synthetic data with known distributions for benchmarking and experimental data obtained from TiOx ReRAM devices for practical testing. Novel device metrics are proposed, and it is shown that these metrics can present crucial insights on the device population prior to training the hardware network. Results on a multi-layer perceptron trained on MNIST show that device models based on binning deviate from target network accuracy at a low number of points and high switching noise in the device dataset. The proposed approach opens the possibility for device-algorithm co-design investigations into statistical device models with better performance, as well as experimentally verified modeling bias in different in-memory computing and neural network architectures.

In-memory computing with emerging memory devices: Status and outlook

In-memory computing (IMC) has emerged as a new computing paradigm able to alleviate or suppress the memory bottleneck, which is the major concern for energy efficiency and latency in modern digital computing. While the IMC concept is simple and promising, the details of its implementation cover a broad range of problems and solutions, including various memory technologies, circuit topologies, and programming/processing algorithms. This Perspective aims at providing an orientation map across the wide topic of IMC. First, the memory technologies will be presented, including both conventional complementary metal-oxide-semiconductor-based and emerging resistive/memristive devices. Then, circuit architectures will be considered, describing their aim and application. Circuits include both popular crosspoint arrays and other more advanced structures, such as closed-loop memory arrays and ternary content-addressable memory. The same circuit might serve completely different applications, e.g., a crosspoint array can be used for accelerating matrix-vector multiplication for forward propagation in a neural network and outer product for backpropagation training. The different algorithms and memory properties to enable such diversification of circuit functions will be discussed. Finally, the main challenges and opportunities for IMC will be presented.

Hardware-Intrinsic Physical Unclonable Functions by Harnessing Nonlinear Conductance Variation in Oxide Semiconductor-Based Diode

With the advancement of the Internet of Things (IoT), numerous electronic devices are connected to each other and exchange a vast amount of data via the Internet. As the number of connected devices increases, security concerns have become more significant. As one of the potential solutions for security issues, hardware intrinsic physical unclonable functions (PUFs) are emerging semiconductor devices that exploit inherent randomness generated during the manufacturing process. The unclonable security key generated from PUF can address the inherent limitations of conventional electronic systems which depend solely on software. Although numerous PUFs based on the emerging memory devices requiring switching operations have been proposed, achieving hardware intrinsic PUF with low power consumption remains a key challenge. Here, we demonstrate that the process-induced nonlinear conductance variations of oxide semiconductor-based Schottky diodes provide a suitable source of entropy for the implementation of PUF without switching operation. Using a mild oxygen plasma treatment, the surface electron accumulation layer that forms naturally in oxide semiconductor film can be partially eliminated, resulting in a large variation of nonlinearity as an exotic entropy source. The mild plasma-treated Schottky diodes showed near ideal 50% average uniformity and uniqueness, as well as an ideal entropy value without the need for additional hardware area and power costs. These findings will pave the way for the development of hardware intrinsic PUFs to realize energy-efficient cryptographic hardware.

Sub-10 fJ/bit radiation-hard nanoelectromechanical non-volatile memory

With the exponential growth of the semiconductor industry, radiation-hardness has become an indispensable property of memory devices. However, implementation of radiation-hardened semiconductor memory devices inevitably requires various radiation-hardening technologies from the layout level to the system level, and such technologies incur a significant energy overhead. Thus, there is a growing demand for emerging memory devices that are energy-efficient and intrinsically radiation-hard. Here, we report a nanoelectromechanical non-volatile memory (NEM-NVM) with an ultra-low energy consumption and radiation-hardness. To achieve an ultra-low operating energy of less than 10 {{{{{{rm{fJ; bit}}}}}}}^{-1}, we introduce an out-of-plane electrode configuration and electrothermal erase operation. These approaches enable the NEM-NVM to be programmed with an ultra-low energy of 2.83 {{{{{{rm{fJ; bit}}}}}}}^{-1}. Furthermore, due to its mechanically operating mechanisms and radiation-robust structural material, the NEM-NVM retains its superb characteristics without radiation-induced degradation such as increased leakage current, threshold voltage shift, and unintended bit-flip even after 1 Mrad irradiation.

A Co-Designed Neuromorphic Chip With Compact (17.9K F2) and Weak Neuron Number-Dependent Neuron/Synapse Modules.

Many efforts have been made to improve the neuron integration efficiency on neuromorphic chips, such as using emerging memory devices and shrinking CMOS technology nodes. However, in the fully connected (FC) neuromorphic core, increasing the number of neurons will lead to a square increase in synapse & dendrite costs and a high-slope linear increase in soma costs, resulting in an explosive growth of core hardware costs. We propose a co-designed neuromorphic core (SRCcore) based on the quantized spiking neural network (SNN) technology and compact chip design methodology. The cost of the neuron/synapse module in SRCcore weakly depends on the neuron number, which effectively relieves the growth pressure of the core area caused by increasing the neuron number. In the proposed BICS chip based on SRCcore, although the neuron/synapse module implements 1∼16 times of neurons and 1∼66 times of synapses, it only costs an area of 1.79 × 107 F2, which is 7.9%∼38.6% of that in previous works. Based on the weight quantization strategy matched with SRCcore, quantized SNNs achieve 0.05%∼2.19% higher accuracy than previous works, thus supporting the design and application of SRCcore. Finally, a cross-modeling application is demonstrated based on the chip. We hope this work will accelerate the development of cortical-scale neuromorphic systems.

In-memory computing with emerging memory devices: status and outlook

In-memory computing with emerging memory devices: status and outlook

In-memory computing with emerging memory devices: status and outlook

In-memory computing with emerging memory devices: status and outlook

In-memory computing with emerging memory devices: status and outlook

In-memory computing with emerging memory devices: status and outlook

Significant improvement of endurance of Si FeFET through minor hysteresis loop and narrow write pulse width

The HfO2-based Si ferroelectric field-effect transistor has been proposed as an emerging memory device due to its low write power, high speed, CMOS compatibility, and scalability. While the poor endurance limits its application, which is attributed to charge trapping and defect generation. In this work, we investigate the effect of the minor loop operation on defect generation. We find that using a minor loop operation, the trap generation is suppressed, which is quantitively extracted by the low-frequency noise method. We get the endurance of 6 × 107 cycles for Si FeFET with a Hf0.5Zr0.5O2 ferroelectric layer through minor hysteresis loop operation.

Review on data-centric brain-inspired computing paradigms exploiting emerging memory devices

Biologically-inspired neuromorphic computing paradigms are computational platforms that imitate synaptic and neuronal activities in the human brain to process big data flows in an efficient and cognitive manner. In the past decades, neuromorphic computing has been widely investigated in various application fields such as language translation, image recognition, modeling of phase, and speech recognition, especially in neural networks (NNs) by utilizing emerging nanotechnologies; due to their inherent miniaturization with low power cost, they can alleviate the technical barriers of neuromorphic computing by exploiting traditional silicon technology in practical applications. In this work, we review recent advances in the development of brain-inspired computing (BIC) systems with respect to the perspective of a system designer, from the device technology level and circuit level up to the architecture and system levels. In particular, we sort out the NN architecture determined by the data structures centered on big data flows in application scenarios. Finally, the interactions between the system level with the architecture level and circuit/device level are discussed. Consequently, this review can serve the future development and opportunities of the BIC system design.