Multi-core Embedded System Research Articles

Optimizing the data placement and scheduling on multi-port DWM in multi-core embedded system

Applications run in embedded systems should usually be completed within the constrained time to reduce energy consumption. Therefore, the memory of embedded system should satisfy time-efficient and energy-efficient. Domain Wall Memory (DWM) achieves high energy efficiency, high density, non-volatile and low cost advantages. However, the data access on DWM always requires shift operations to align the domain with the port which can access the data in the domain. In the case that there are multi-core processors with multi-port DWM, the data placement and scheduling, therefore, can extremely affect the parallelism, total execution time and performance. In this paper, we handle the data placement and scheduling on multi-port DWM in multi-core system (DPSMDMS), and provide the integer linear programming (ILP) algorithm to solve this problem optimally. What is more, we propose a layering and grouping for data placement and scheduling (LGPS) heuristic algorithm to get the approximate optimal solution in polynomial time. In benchmarks, the experimental results show that ILP and LGPS reduce on average 64.6% and 64.8% of the total execution time, respectively, compared with the non-optimized strategy.

RETRACTED: Design of sports course management system based on multi-core embedded system and motion capture

With the constant advancement of sports data and data innovation, sports the executives. The framework is essentially changing the impact and impact of sports the board, customary games, the executive's ideas, authoritative structure model, and the executive's strategy, significant issues, such as such games the board, to that venture. Both data innovation, utilization of data innovation, and the usage and improvement of sports, the executives advance one another, advancing. During the time spent, the data, to associate with sports the board. Sports the executive's data is the problem area of exploration identified with the significant substance of the framework sports data and data development based on Artificial Neural Network (ANN). Shrewd implanted frameworks, more modest units, change the advanced inserted frameworks plan, and engineering to meet the low energy utilization's ongoing activity, it ought to be financially savvy. With the utilization of strategies, for example, diminished guidance Systems on Chip (SOC, for example, to Reduced Instruction Set Computing Chips (RISC) framework, it have more space for the web of things. The coming of the Internet things, and applied to existing administrations, has brought an altogether new sort of higher proficiency. Just as application-explicit prerequisites, the gadget's availability and correspondences have presented another test for the nonstop IoT application. We, IoT frameworks, investigates the current pattern, and it is a basic innovation to the advancement of their separation. The primary highlights of the web of things, the fundamental application territories, and the principal research subjects of conversation are a far-reaching Internet the perspective of things for installed framework plans.

A comparison of stereo matching algorithms on multi-core Digital Signal Processor platform

Stereo Matching algorithms reconstruct a depth map from a pair of stereoscopic images. Stereo Matching algorithms are computationally intensive. Implementing efficient stereo matching algorithms on embedded systems is very challenging. This paper compares implementation efficiency and output quality of the state of the art dense stereo matching algorithms on the same multicore embedded system. The three different classes of stereo matching algorithms are local methods, semi-global methods and global methods. This paper compares three algorithms of the literature with a good trade-off between complexity and accuracy : Bilateral Filtering Aggregation (BFA, Local Method), One Dimension Belief Propagation (BP-1D, Semi Global Methods) and Semi Global Matching (SGM, Semi Global Methods). For the same input data the BFA, BP-1D and SGM were fully optimized and parallelized on the C6678 platform and run at respectively 10.7 ms, 4.1 ms and 47.1 ms.

Architecture optimization: speed or accuracy? both!

Embedded systems are becoming more and more complex, thus demanding innovative means to tame their challenging development. Among others, early architecture optimization represents a crucial activity in the development of embedded systems to maximise the usage of their limited resources and to respect their real-time requirements. Typically, architecture optimization seeks good architecture candidates based on model-based analysis. Leveraging abstractions and estimates, this analysis usually produces approximations useful for comparing architecture candidates. Nonetheless, approximations do not provide enough accuracy in estimating crucial extra-functional properties. In this article, we provide an architecture optimization framework that profits from both the speed of model-based predictions and the accuracy of execution-based measurements. Model-based optimization rapidly finds a good architecture candidate, which is refined through optimization based on monitored executions of automatically generated code. Moreover, the framework enables the developer to leverage her optimization experience. More specifically, the developer can use runtime monitoring of generated code execution to manually adjust task allocation at modeling level, and commit the changes without halting execution. In the article, our architecture optimization mechanism is first described from a general point of view and then exploited for optimizing the allocation of software tasks to the processing cores of a multicore embedded system; we target extra-functional properties that can be concretely represented and automatically compared for different architectural alternatives (such as memory consumption, energy consumption, or response-time).

Domain-Specific Programming Environment for Heterogeneous Multicore Embedded Systems

Nowadays embedded systems are used in a broad range of domains such as avionics, space, automotive, mobile, domestic appliances etc. Sophisticated software determines the quality of embedded systems and requires high-qualified experts for software development. Software becomes the main assert of embedded systems that is valuable to retain in changing computing platforms in embedded systems evolution. Computing platforms for embedded systems became multicore processors and SoC, they can change in the embedded system lifetime that could be long (dozen of years for an automobile and airplane). It requires software porting to new platforms as a regular process. Many tools and approaches allow developing of software for domain area experts, but mainly for general-purpose computing systems. In this paper the authors present the complex technology and tools that allows involving domain experts in software development for embedded systems. The proposed technology has various aspects and abilities that can be used to build verifiable and portable software for a wide range of embedded platforms.

Research on Improved Genetic Algorithm

An improved genetic algorithm for the function optimization of multi-core embedded system is proposed. A number of chromosomes that distribute uniformly in space are generated by the algorithm randomly. Each chromosome is randomly coded and a new one will be generated by mutual calculation. After continuous elimination and circulation, the optimized chromosomes can be selected. The improved algorithm makes the mutation offspring have the opportunity to be the next parent with the increase of mutation. It enhances the parent diversity, increases the crossover rate, activates crossover between the parents and has chance to access to the best solution. The efficiency and cost reduction performance are improved. The different tasks will be distributed in parallel to available processors so as to meet the real-time requirements.

Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Minimization of power dissipation can be considered at algorithmic, compiler, architectural, logic, and circuit level. Recent research trends for multicore programming models have come to the direction that parallel design patterns can be a solution to develop multicore applications. As parallel design patterns are with regularity, we view this as a great opportunity to exploit power optimizations in the software layer. In this paper, we investigate compilers for low power with parallel design patterns on embedded multicore systems. We evaluate four major parallel design patterns, Pipe and Filter, MapReduce with Iterator, Puppeteer, and Bulk Synchronous Parallel (BSP) Model. Our work attempts to devise power optimization schemes in compilers by exploiting the opportunities of the recurring patterns of embedded multicore programs. The proposed optimization schemes are rate-based optimization for Pipe and Filter pattern , early-exit power optimization for MapReduce with Iterator pattern, power aware mapping algorithm for Puppeteer pattern, and multi-phases power gating scheme for BSP pattern. In our experiments, real world multicore applications are evaluated on a multicore power simulator. Significant power reductions are observed from the experimental results. Therefore, we present a direction for power optimizations that one can further identify additional key design patterns for embedded multicore systems to explore power optimization opportunities via compilers.

Design Issues in a Performance Monitor for Embedded Multi-core Systems

Multi-core processors have elevated the performance of software via true parallelization. However, this has also created new challenges. One serious issue is the bottleneck in system performance due to synchronization, cache misses, or resource starvation, which is hard to detect in application software with runtime changing behavior. Performance monitors are usually employed for such detection. Nevertheless, monitors have introduced their own computation and communication overheads, especially in embedded multi-core systems. In this work, we propose a multi-core performance monitor and evaluate the effects of monitor overheads on different types of tasks, such as CPU-bound and IO-bound tasks. Further, we give suggestions on the number of monitors and the type of monitor deployments for embedded multi-core applications. Besides trying to reduce monitor overheads, we also aim at the accuracy and the immediacy of the monitored information. Through a real-world example, namely digital video recording system, we demonstrate how different monitoring periods affect the tradeoff between the accuracy and the immediacy.

Automatic Facial Expression Exaggeration System with Parallelized Implementation on a Multi-Core Embedded Computing Platform

In this paper, we propose an automatic facial expression exaggeration system, which consists of face detection, facial expression recognition, and facial expression exaggeration components, for generating exaggerated views of different expressions for an input face video. In addition, the parallelized algorithms for the automatic facial expression exaggeration system are developed to reduce the execution time on a multi-core embedded system. The experimental results show satisfactory expression exaggeration results and computational efficiency of the automatic facial expression exaggeration system under cluttered environments. The quantitative experimental comparisons show that the proposed parallelization strategies provide significant computational speedup compared to the single-processor implementation on a multi-core embedded platform.

Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems

A novel high throughput and scalable unified architecture for the computation of the transform operations in video codecs for advanced standards is presented in this paper. This structure can be used as a hardware accelerator in modern embedded systems to efficiently compute all the two-dimensional 4 × 4 and 2 × 2 transforms of the H.264/AVC standard. Moreover, its highly flexible design and hardware efficiency allows it to be easily scaled in terms of performance and hardware cost to meet the specific requirements of any given video coding application. Experimental results obtained using a Xilinx Virtex-5 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which presents a throughput per unit of area relatively higher than other similar recently published designs targeting the H.264/AVC standard. Such results also showed that, when integrated in a multi-core embedded system, this architecture provides speedup factors of about 120× concerning pure software implementations of the transform algorithms, therefore allowing the computation, in real-time, of all the above mentioned transforms for Ultra High Definition Video (UHDV) sequences (4,320 × 7,680 @ 30 fps).

A Pattern-based Refactoring Approach for Multi-core System Design

Until recently, the most software development tools and techniques were concentrated on views from the sequential model of program execution. Software developers who only familiarize with the sequential model will face unusual challenges of software projects that require multi-core or parallel programming. In this paper, we addresses the challenges that developers face as their projects requiring multi-core or parallel programming by applying design patterns. In general, design patterns are usually regarded as the role of quality-improver for improving software quality, but they could be the role of design-facilitator for facilitating design activities. To address this issue, we propose an approach for specifying the applicable contexts and refactoring steps of patterns systematically, as well as automating the refactoring process for lightening the burden of developers. We also extract a multi-core pattern ParallelWhile which is derived from the template class parallel_while of Intel ® TBB library to introduce our approach. Furthermore, we demonstrate our approach by a real-world multicore embedded system PVE (Parallel Video Encoder), where Command Pipeline pattern is designed for the design enhancement and platform migration. It aids developers identifying operations which could be parallel processing, and revising a sequential design as an Intel ® TBB parallel structure. In addition, our approach can promote the extensibility of parallel operations.

Maintaining I/O Data Coherence in Embedded Multicore Systems

In embedded systems, multiple cores mean multiple caches and often multiple cache levels. Consequently, maintaining coherency between the cores' caches and the data generated or consumed by I/O devices is challenging, with different solutions trading off hardware versus software complexity. The optimal approach for I/O data coherence depends on application and system characteristics, and might require a combination of techniques.