Optimizing the data placement and scheduling on multi-port DWM in multi-core embedded system

Abstract

Applications run in embedded systems should usually be completed within the constrained time to reduce energy consumption. Therefore, the memory of embedded system should satisfy time-efficient and energy-efficient. Domain Wall Memory (DWM) achieves high energy efficiency, high density, non-volatile and low cost advantages. However, the data access on DWM always requires shift operations to align the domain with the port which can access the data in the domain. In the case that there are multi-core processors with multi-port DWM, the data placement and scheduling, therefore, can extremely affect the parallelism, total execution time and performance. In this paper, we handle the data placement and scheduling on multi-port DWM in multi-core system (DPSMDMS), and provide the integer linear programming (ILP) algorithm to solve this problem optimally. What is more, we propose a layering and grouping for data placement and scheduling (LGPS) heuristic algorithm to get the approximate optimal solution in polynomial time. In benchmarks, the experimental results show that ILP and LGPS reduce on average 64.6% and 64.8% of the total execution time, respectively, compared with the non-optimized strategy.