Embedded Computer Systems Research Articles

Wireless Body Sensor Network in Health Maintenance Systems

Health Maintenance systems are a special monitoring systems of the basic life functions. The goal of the work was to design and realize the wireless body sensor networks for on line vital function monitoring. The system is based on wireless sensors, information technologies and embedded computer systems. The man uses modified places where the monitoring systems that watch movement, position and chosen life functions are installed. In this case all the information about person's basic life functions and geographical location transmitted by wireless technology. All the measuring devices communicate with embedded microprocessor system wireless by Bluetooth or ZigBee technology. Ill. 3, bibl. 9 (in English; abstracts in English and Lithuanian). http://dx.doi.org/10.5755/j01.eee.115.9.762

Caches and Predictors for Real-Time, Unobtrusive, and Cost-Effective Program Tracing in Embedded Systems

The increasing complexity of modern embedded computer systems makes software development and system verification the most critical steps in system development. To expedite verification and program debugging, chip manufacturers increasingly consider hardware infrastructure for program debugging and tracing, including logic to capture and filter traces, buffers to store traces, and a trace port through which the trace is read by the debug tools. In this paper, we introduce a new approach to capture and compress program execution traces in hardware. The proposed trace compressor encompasses two cost-effective structures, a stream descriptor cache, and a last stream predictor. Information about the program flow is translated into a sequence of hit and miss events in these structures, thus dramatically reducing the number of bits that need to be sent out of the chip. We evaluate the efficiency of the proposed mechanism by measuring the trace port bandwidth on a set of benchmark programs. Our mechanism requires only 0.15 bits/instruction/CPU on average on the trace port, which is a sixfold improvement over state-of-the-art commercial solutions. The trace compressor requires an on-chip area that is equivalent to one third of a 1 kilobyte cache and it allows for continual and unobtrusive program tracing in real time.

Study on the Implementation Method of Data Review for a Certain Weapon System in VxWorks

In the researching and using process of a certain large weapon system, the practical navigation data was the most important and effective way for the system analysis and the fault reoccurrence. Aiming at the characteristics of the weapon launching and control system such as multiple data types, complex data property, and complex data management, the embedded computer system based on VxWorks is used in this article to realize the review of multiple kinds of data by the timer interrupt mode, and through relative experiments, the result showed that the real-time review system of the large-capacity practical navigation data designed in this article was effective and reliable, completely fulfilling the design requirements.

Soft-computing methods for robust authentication using soft-biometric data

Biometrics is the measurement of person’s physiological or behavioral characteristics. It enables authentication of a person’s identity using such measurements. Biometric-based authentication is thus becoming increasingly important in computer-based applications because the amount of sensitive data stored in such systems is growing. Particularly challenging is the implementation of biometric-based authentication in embedded computer system applications, because the resources of such systems are scarce. Reliability and performance are two primary requirements to be satisfied in embedded system applications. Single-mode and hard-feature-based biometrics do not offer enough reliability and performance to satisfy such requirements. Multimode biometrics is a primary level of improvement. Soft-biometric features can thus be considered along with hard-biometric features to further improve performance. A combination of soft-computing methods and soft-biometric data can yield more improvements in authentication performance by limiting requirements for memory and processing power. The multi-biometric approach also increases system reliability, since most embedded systems can capture more than one physiological or behavioral characteristic. A multi-biometric platform that combines voiceprint and fingerprint authentication was developed as a reference model to demonstrate the potential of soft-computing methods and soft-biometric data. Hard-computing pattern-matching algorithms were applied to match hard-biometric features. Artificial neural network (ANN) processing was applied to match soft-biometric features. Both hard-computing and soft-computing matching results are inferred by a fuzzy logic engine to perform smart authentication using a decision-fusion paradigm. The embedded implementation was based on a single-chip, floating-point, digital signal processor (DSP) to demonstrate the practical embeddability of such an approach and the improved performance that can be attained despite limited system resources.

Development of New Apparatus for Slug Detection on the Loom

There are lots of slugs produced in weaving process, which seriously affects the quality of silk products. In this study, red pulse laser was used as the signal source. Light signal goes through the shed, then enter the ARM (Advanced RISC Machines) embedded computer systems for analysis. Thus the slug situation of shed state is judged and the loom is controlled to make corresponding adjustments to prevent more slug formation. Plenty of tests are carried out on various slugs and satisfied results are gained. It shows that using ARM to develop the Loom Slug Detection Apparatus is feasible.

A study of self-propagating mal-packets in sensor networks: Attacks and defenses

Since sensor applications are implemented in embedded computer systems, cyber attacks that compromise regular computer systems via exploiting memory-related vulnerabilities present similar threats to sensor networks. However, the paper shows that memory fault attacks in sensors are not the same as in regular computers due to sensor’s hardware and software architecture. In contrast to worm attacks, mal-code carried by exploiting packets cannot be executed in sensors built upon Harvard architecture. Therefore, the paper proposes a range of attack approaches to illustrate that a mal-packet, which only carries specially crafted data, can exploit memory-related vulnerabilities and utilize existing application code in a sensor to propagate itself without disrupting the sensor’s functionality. The paper shows that such a mal-packet can have as few as 17 bytes. A prototype of a 27-byte mal-packet has been implemented and tested in Mica2 sensors. Simulation shows that the propagation pattern of such a mal-packet in a sensor network is very different from worm propagation. Mal-packets can either quickly take over the whole network or hardly propagate under different traffic situations. The paper also develops two defense schemes (S2Guard and S2Shuffle) based on existing defense techniques to protect sensor applications. The analysis shows that they only incur a little overhead and can stop the propagation of mal-packets.

Transparent Proxy for Secure E-Mail

Transparent Proxy for Secure E-MailThe paper deals with the security of e-mail messages and e-mail server implementation by means of a transparent SMTP proxy. The security features include encryption and signing of transported messages. The goal is to design and implement a software proxy for secure e-mail including its monitoring, administration, encryption and signing keys administration. In particular, we focus on automatic public key on-the-fly encryption and signing of e-mail messages according to S/MIME standard by means of an embedded computer system whose function can be briefly described as a brouter with transparent SMTP proxy.

Research on Reconfigurable High-Speed Serial Bus Used in High-Reliability Embedded Computer

The characteristics and limitations of the buses, which are widely used nowadays, are analyzed in this paper. Because these buses don’t adapt to the high-reliability embedded computer system, a novel bus is proposed which is characterized by its high-reliability. And its capacity is reached through its unique datum’s dynamic reconfiguration mechanism. The basic architecture and communication protocol are presented in this paper. And then the key points during realization of this bus are discussed. Finally, the probably application scope and prospects are indicated.

Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems

Multi-objective evolutionary algorithms (MOEAs) have received increasing interest in industry because they have proved to be powerful optimizers. Despite the great success achieved, however, MOEAs have also encountered many challenges in real-world applications. One of the main difficulties in applying MOEAs is the large number of fitness evaluations (objective calculations) that are often needed before an acceptable solution can be found. There are, in fact, several industrial situations in which fitness evaluations are computationally expensive and the time available is very short. In these applications efficient strategies to approximate the fitness function have to be adopted, looking for a trade-off between optimization performance and efficiency. This is the case in designing a complex embedded system, where it is necessary to define an optimal architecture in relation to certain performance indexes while respecting strict time-to-market constraints. This activity, known as design space exploration (DSE), is still a great challenge for the EDA (electronic design automation) community. One of the most important bottlenecks in the overall design flow of an embedded system is due to simulation. Simulation occurs at every phase of the design flow and is used to evaluate a system which is a candidate for implementation. In this paper we focus on system level design, proposing an extensive comparison of the state-of-the-art of MOEA approaches with an approach based on fuzzy approximation to speed up the evaluation of a candidate system configuration. The comparison is performed in a real case study: optimization of the performance and power dissipation of embedded architectures based on a Very Long Instruction Word (VLIW) microprocessor in a mobile multimedia application domain. The results of the comparison demonstrate that the fuzzy approach outperforms in terms of both performance and efficiency the state of the art in MOEA strategies applied to DSE of a parameterized embedded system.

Security extensions for integrity and confidentiality in embedded processors

With current trends toward embedded computer systems’ ubiquitous accessibility, connectivity, diversification, and proliferation, security becomes a critical issue in embedded computer systems design and operation. Embedded computer systems are subjected to both software and physical attacks aimed at subverting system operation, extracting key secrets, or intellectual property theft. We propose several cost-effective architectural extensions suitable for mid-range to high-end embedded processors. These extensions ensure the integrity and confidentiality of both instructions and data, introducing low performance overhead (1.86% for instructions and 14.9% for data).

Using a Low-Cost SoC Computer and a Commercial RTOS in an Embedded Systems Design Course

This paper describes the author's experiences using a low-cost system-on-a-chip (SoC) embedded computer system and a commercial real-time operating system (RTOS) in the laboratory component of an undergraduate embedded system design class. The target hardware is a small low-cost X86 SoC computer system that has a wide range of I/O features. For software development, a popular commercial hard RTOS is used that has been designed for use in embedded devices. This course covers both hardware and software topics in embedded systems, and the course culminates in a final team-based design project. A full set of course materials including a textbook with laboratory tutorials, instructor slides, and code examples has been developed and is available online in electronic form.

Introduction to the Special Issue on SAMOS 2007

This special issue includes a selection of the best papers from the 2007 SAMOS VII Symposium. The International Symposium on Embedded Computer Systems, Architectures, Modeling and Simulation (SAMOS) is an event which annually takes place on the scenic Mediterranean island of Samos. It comprises two co-located events—the International SAMOS Conference and the SAMOS Workshop. In 2007 more than 200 papers were submitted for these two events. After a very competitive selection process only about 30% of these papers have been selected for presentation. According to the Symposium’s ranked results and the results of a second stage review process of all presentations from SAMOS, the following eight papers related to architectures and implementations of embedded systems have been selected for publication in this special issue. We would like to thank all reviewers of the SAMOS Workshop and particularly all reviewers of this special issue for their detailed and intensive review work. The investment of their time and insight is very much appreciated and helped to generate this selection of high quality technical papers. The important field of Digital Signal Processor Architectures which is classically one of the focus topics of SAMOS is covered in this special issue by three papers: Thuresson et al. present a paper which is entitled “FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.” Within this paper the authors present a highly efficient DSP architecture and discuss specific elements of this architecture including fine-grained control and a flexible interconnect which lead to significant speedups and significant energy savings. They elaborated on their flexible interconnect that allows the datapath to be dynamically reconfigured as a consequence of code generation. Additionally, the FlexCore provides specialized datapath units to be inserted and utilized within the same architecture and compilation framework. The problem of memory bottlenecks in modern DSP architectures is addressed by the paper of Pitkaenen et al. which is entitled “Parallel Memory Architecture for Application-Specific Instruction-Set Processors.” In this paper, a conflict resolving parallel data memory system for application-specific instruction-set processors is described. The memory structure is generic and reusable to support various application-specific designs. The proposed parallel memory system is attached to an ASIP core and comparisons on area, power, and critical path are presented. Significant power savings can be obtained by exploiting their parallel memory system instead of multi-port memories. Memory access problems are also addressed in the paper of Galuzzi et al. In “High-bandwidth Address Generation Unit” they present an efficient data fetch circuit to retrieve several operands from an n-way interleaved memory system in a single machine cycle. The proposed address generation unit operates with an improved version of a low-order interleaved memory access approach. The presented design supports data structures of arbitrary lengths and various odd strides. J Sign Process Syst (2009) 57:1–3 DOI 10.1007/s11265-008-0220-8

Towards Design Space Exploration for Biological Systems

For both embedded systems and biological cell systems, design is a feature that defines their identity. The assembly of different components in designs of both systems can vary widely. Given the similarities between computers and cellular systems, methods and models of computation from the domain of computer systems engineering could be applied to model cellular systems. Our aim is to construct a framework that focuses on understanding the design options and consequences within a cell, taking an in-silico (forward-) engineering approach rather than the reverse-engineering approach now used by default in this domain. We take our ideas from the domain of embedded computer systems. The most important features of our approach, as taken from this domain, are a variable abstraction level of model components that allows for inclusion of components of which detailed information is lacking, and a separation of concerns between function and performance by components in the design. This allows for efficient and flexible modeling. Also, there is a strict separation between computation within and communication between components, thus reducing complexity. As a proof-of-principle, we show that we can make a statement regarding the design of the gene expression machinery of a cell to produce a protein, using such a method.

Taking the example of computer systems engineering for the analysis of biological cell systems

In this paper, we discuss the potential for the use of engineering methods that were originally developed for the design of embedded computer systems, to analyse biological cell systems. For embedded systems as well as for biological cell systems, design is a feature that defines their identity. The assembly of different components in designs of both systems can vary widely. In contrast to the biology domain, the computer engineering domain has the opportunity to quickly evaluate design options and consequences of its systems by methods for computer aided design and in particular design space exploration. We argue that there are enough concrete similarities between the two systems to assume that the engineering methodology from the computer systems domain, and in particular that related to embedded systems, can be applied to the domain of cellular systems. This will help to understand the myriad of different design options cellular systems have. First we compare computer systems with cellular systems. Then, we discuss exactly what features of engineering methods could aid researchers with the analysis of cellular systems, and what benefits could be gained.

The Bremen ocean bottom tiltmeter (OBT) – a technical article on a new instrument to monitor deep sea floor deformation and seismicity level

The Bremen ocean bottom tiltmeter is a new 6000 m-depth deep sea instrument for autonomous observation of sea floor tilt with signal periods longer than 7.5 s. The instrument also records vertical acceleration in the frequency range from DC to 1 Hz. The tiltmeter has an Applied Geomechanics Inc. 756 wide angle biaxial bubble tilt sensor with a resolution of 1.0μ rad (0.2 arc second). A Kistler Corp. MEMS accelerometer of type Servo K-Beam 8330A2.5 with about 10−5m/s2 resolution is used for the acceleration measurements. An Oceanographic Embedded Systems AD24 24 bit Sigma-Delta converter, which is controlled by a low-power Persistor Inc. embedded computer system of type CF 2, samples the data. The duration of tiltmeter operation is more than one year, which is controlled by the battery life. In our design the tiltmeter does not need active leveling devices, i.e., servo motors or other moving components to adjust sensors or frame. We designed the instrument for deployments by means of a remote operated vehicle. Since May 2005 the Bremen ocean bottom tiltmeter has recorded sea floor deformation and seismicity level in the Logatchev hydrothermal vent field, Mid-Atlantic Ridge. The tiltmeter is a part of the monitoring system of project ‘Logatchev Long-Term Environmental Monitoring,’ called LOLEM, of the German research program with the name ‘Schwerpunktprogramm 1144: Vom Mantel zum Ozean.’

Habitar digital, arquitectura sensible al hombre

Arquitectura interactiva es un concepto que cada vez más se extiende desde el área de la informática al diseño espacial. Este artículo presenta tres casos en los cuales es posible evidenciar, como a diferentes escalas la incorporación de tecnologías computacionales en el espacio están generando nuevas plataformas digitales y de sociabilización.

6.3.4 Impact of Embedded Software Technology on Systems Engineering

AbstractSystems such as aircraft and consumer electronics have included embedded computers in their designs for several decades now. In these systems, software was usually treated as a component inside a box much the same way you would treat a circuit card assembly or a power supply. Requirements would flow down to the box specification and the box specification would then flow down to the components inside the box. But recently, several trends are changing the relationship between embedded software and the system as a whole. Many embedded computer systems now use network protocols and infrastructures similar to information systems deployed on commodity hardware. Systems with embedded computers now have expectations and requirements for extensibility similar to those of information systems where methodologies for extensibility are well established. But unlike information systems, systems with embedded software often have complex non‐software elements and the software is not loosely coupled with the hardware. These systems require a synthesis of approaches.

The control system for the front-end electronics of the ALICE time projection chamber

The ALICE detector is a dedicated heavy-ion detector currently built at the Large Hadron Collider (LHC) at CERN. The detector control system (DCS) covers the task of controlling, configuring and monitoring the detector. One sub-system is the control system for the Front-end electronics of the time projection chamber (TPC). It controls in total 216 readout systems with 4356 Front-End Cards serving roughly 560 000 channels. The system consists of a large number of distributed nodes in a layer-structured hierarchy. The low-level node controlling the Front-end electronics is an embedded computer system, the DCS board, which provides the opportunity to run a light-weight Linux system on the card. The board interfaces to the Front-end electronics via a dedicated hardware interface and connects to the higher DCS-layers via the DIM communication framework over Ethernet. Since the experiment will be running in a radiation environment, fault tolerance, error correction and system stability in general are major concerns. Already the low level devices carry out intelligent error handling and act automatically upon several conditions. This paper presents the architecture of the system, the application of the DCS board and experiences from integration tests.

Enhancing the performance of radiation-hardened embedded computer systems

Adaptive clock-rate switching is discussed in terms of enhancing the performance of radiation-hardened embedded computer systems. Clock rate is optimized by evaluating the closeness of the current failure rate to its maximum allowable level.

Instruction code mapping for performance increase and energy reduction in embedded computer systems

In this paper, we present a novel and fast constructive technique that relocates the instruction code in such a manner into the main memory that the cache is utilized more efficiently. The technique is applied as a preprocessing step, i.e., before the code is executed. Our technique is applicable in embedded systems where the number and characteristics of tasks running on the system is known a priori. The technique does not impose any computational overhead to the system. As a result of applying our technique to a variety of real-world applications we observed through simulation a significant drop of cache misses. Furthermore, the energy consumption of the whole system (CPU, caches, buses, main memory) is reduced by up to 65%. These benefits could be achieved by a slightly increased main memory size of about 13% on average.