Elmore Delay Research Articles

An innovative interconnect structure with improved Elmore delay estimation model for deep submicron technology

An innovative interconnect structure with improved Elmore delay estimation model for deep submicron technology

A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects

With extreme miniaturization of traditional CMOS devices in deep sub-micron design levels, the delay of a circuit, as well as power dissipation and area are dominated by interconnections between logic blocks. Interconnect today is causing major problems such as delay, power dissipation, and so on. In an attempt to search for alternative materials, Graphene nanoribbons have been found to be potential for both transistors and interconnects due to its outstanding electrical and thermal properties. Graphene nanoribbons provide better options as materials used for global routing trees in VLSI circuits. However, certain special characteristics of Graphene nanoribbon prohibit direct application of existing VLSI routing tree construction methods. In this article, we address this issue and propose heuristic methods for construction of Graphene nanoribbon--based minimum hybrid cost and minimum-delay Steiner trees. We compute the delays for the trees using Elmore delay approximation. Experimental results demonstrate the effectiveness of our proposed methods, which are quite encouraging.

An Effective Method for Interconnect Delay Optimization of ASIC’s

With the development of integrated circuit design into 65nm process, interconnect delay has become one of the key factors that hinder the convergence of time sequence. Firstly, the determinants of interconnect delay are analyzed by Elmore delay model, and then experiments are carried out at the stage of circuit physical design. Verify the metal layer, metal width, buffer driving ability and buffer number can effectively optimize the interconnect delay.

High speed RLC equivalent RC delay model for global VLSI interconnects

Current-mode signaling significantly is known for increasing the bandwidth of on-chip interconnects and reduces the overall propagation delay. In this paper feature of current mode interconnects is exploited for investigating the performance of RLC equivalent ReffCT mathematical delay model of interconnects. This is due to a simple RC interconnects model which results a significant error in delay estimation. Due to this equivalency the non ideal effect of inductive behavior at high frequencies and scaled technologies can be suppressed. The dominance of inductance effect is optimized by Simulative Sweep Analysis Techniques (SSAT). Accuracy is verified by analytical and SPICE simulation results. The performance of delay model is further estimated for voltage and current mode interconnects. When test results are estimated with voltage and current mode systems, it is observed that the equivalent model is superior to the traditional Elmore and Sakurai delay model.

An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC

Effective clock tree design is an important factor for determining chip performance. In this study, the authors present a 3D clock tree design algorithm to enhance the speed and performance of a VLSI chip. The authors propose an algorithm to determine the performance of the clock network by optimising both the clock skew and the dynamic power consumption of the 3D IC clock tree. The authors propose an algorithm for clock tree design based on the Elmore Delay method and routes all the sinks efficiently considering the obstacles with the use of an optimum number of through-silicon-vias (TSVs). The proposed method starts with a segregation technique to divide the sinks into smaller zones. Subsequently, an obstacle avoiding abstract clock tree is constructed with a minimum number of TSVs and buffers. The skew and dynamic power of the tree is calculated. Consequently, the proposed method is compared with recent existing works. The experimental results so obtained are quite encouraging.

Global Routing With Timing Constraints

We show how to incorporate global static timing constraints into global routing. Our approach is based on the min–max resource sharing model that proved successful for global routing in theory and practice. Static timing constraints are modeled by a linear number of additional resources and customers. The algorithm dynamically adjusts delay budgets and can, thus, tradeoff wiring congestion for delay. As a subroutine, the algorithm routes a single net. If this subroutine is near-optimal, we will find near-optimal solutions for the overall problem very efficiently. The approach works for many delay models; here we discuss a linear delay model (before buffering) and the Elmore delay model (after buffering). We demonstrate the benefit of our timing-constrained global routing algorithm by experimental results on industrial chips.

Modeling and Analysis of Passive Switching Crossbar Arrays

Emerging technologies have enabled efficient, high-speed realizations of ultra-dense crossbar arrays, driving the need for better insight in the transient operation of such systems. Previous work focused mostly on the effect of line resistance and its impact on steady-state response. In this paper, we develop a compact $RC$ framework that includes the effects of parasitics. We use memristors as an exemplar device where interconnect parasitics (resistance, inductance, capacitance, and conductance) are extracted using ANSYS Q3D extractor for 5- and 50- $nm$ feature sizes. A model for the crossbar is presented, considering the stray and coupling capacitive parasitics of the crossbar. The derived model is based on state-space representation and provides more insight into the behavior of crossbar arrays containing either linear or nonlinear switching devices. The framework provides a closed-form solution to evaluate Elmore delay, as well as the steady-state response of the system. Signal delay is evaluated and compared for both grounded and floating interconnect inputs and verified against HSPICE, showing a perfect match.

Steiner Trees with Bounded RC-Delay

We consider the Minimum Elmore Delay Steiner Tree Problem, which is a key problem in VLSI design: We are given a set of pins which have to be connected by a Steiner tree. One of the pins is the source. Challenging timing constraints impose tight bounds on the delay of propagating a signal from the source to the other pins. The commonly used measure is Elmore delay (Elmore in J Appl Phys 19:55---63, 1948). We consider two variants: minimizing the maximum Elmore delay or a weighted sum of Elmore delays. Both variants are strongly NP-hard even for very restricted special cases. Although it is a central problem in VLSI design (Kahng and Robins in On optimal interconnections for VLSI. Kluwer, Boston, 1995; Korte and Vygen in Building bridges--between mathematics and computer science. Springer, Berlin, pp 333---368, 2008), no approximation algorithms were known so far. In this work, we give the first constant-factor approximation algorithm. It works for both variants. The algorithm achieves an approximation ratio of 3.39 in the rectilinear plane and 4.11 in general metric spaces. We can show that our algorithm is best possible in a certain sense. We also demonstrate that our algorithm leads to improvements on real world VLSI instances compared to the currently used standard method of computing short Steiner trees.

Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs

Due to the inappropriate assignment of bump pads or the improper assignment of I/O buffers, the constructed buffered I/O signals in an area-I/O flip-chip design may yield longer maximum delay. In this article, the problem of assigning performance-driven buffered I/O signals in an area-I/O flip-chip design is first formulated. Furthermore, the assignment of the buffered I/O signals can be divided into two sequential phases: Construction of performance-driven I/O signals and Assignment of timing-constrained I/O buffers. Finally, an efficient matching-based approach is proposed to construct the performance-driven I/O signals for the given I/O pins and assign the timing-constrained I/O buffers into the constructed I/O signals in the assignment of the buffered I/O signals in an area-I/O flip-chip design. Compared with the experimental results of seven tested circuits in the Elmore delay model, the experimental results show that the matching-based assignment in our proposed approach can reduce 3.56% of the total path delay, 9.72% of the maximum input delay, 5.90% of the input skew, 5.64% of the maximum output delay, and 6.25% of the output skew on average by reassigning the I/O buffers. Our proposed approach can further reduce 38.89% of the total path delay, 44.00% of the maximum input delay, 49.13% of the input skew, 44.93% of the maximum output delay, and 50.82% of output skew on average by reconstructing the I/O signals and reassigning the I/O buffers into the I/O signals. Compared with the experimental results of seven tested circuits in Peng's [Peng et al. 2006] publication, the experimental results show that our proposed matching-based approach can further reduce 71.06% of the total path delay, 67.83% of the maximum input delay, 59.84% of the input skew, 68.87% of the maximum output delay, and 61.46% of the output skew on average. On the other hand, compared with the experimental results of five tested circuits in Lai's [Lai and Chen 2008] publication, the experimental results show that our proposed approach can further reduce 75.36% of the total path delay, 48.94% of the input skew, and 52.80% of the output skew on the average.

Power Efficient 3D Clock Distribution Network Design with TSV Count Optimization

This paper mainly focuses on power efficient and low skew clock network design for three-dimensional ICs based on through- silicon via (TSV). Clock tree synthesis is carried out in two major steps; 1) 3D Abstract clock tree generation; 2) buffering with skew and slew consideration. Firstly we design abstract clock tree by using(3D-MMM) followed by skew and slew aware buffer insertion. We analyze how the inclusion of TSVs will affect RC parasitic of an otherwise 2D clock network design by studying Elmore Delay model for 3D topology. We propose extension to the Exact Zero Skew (EEZE- Extended Exact Zero Skew) algo- rithm by Dr. Tsay for 3D topology which considers TSV resistance-capacitance. This algorithm designs the clock tree by using optimum number of TSVs suitable for the circuit. This is accomplished by merging cost comparison between sets obtained after 3D MMM implementation. This showed 19% to 23% reduction in wire-length. Spice analysis of the obtained clock network resulted in 16% to 18% reduction in clock power dissipation. This indicates that, 1) With optimum TSV count, wire-length of the clock tree reduces by the considerable amount, 2) Small trade-off between optimal TSV count and wire-length, reduces power dissipation.

IJARCCE - Computer and Communication Engineering

In a high speed digital integrated circuit, annex delay can be momentous and hold for factual exploration by using moments of impulse response delay exploration has been done. Elmore delay is (the first moment of impulse response) interpretation, to moment matching approach which establish reduced order trans-impedance and transfer function approximations. The elmore delay is swift becoming inadequate for deep submicron technologies and reduced order transfer function delays are un-functional for use as early phase design matrices. This paper interpret access for fitting moments of the impulse response to probability density function, so that delay can be appraisal factually for RLC trees, it is a demonstrated that inverse gamma function provides a provable stable approximation. For prolong delay matrices for ramp inputs to the more general and realistic non-step input, we use PERI (probability distribution function extension for ramp input) technology. The factual model consequence compared with MATLAB simulation.

Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC

With no further shrinking of device size, 3-D chip stacking by through-silicon-via (TSV) has been identified as an effective way to achieve better performance in speed and power. However, such solution inevitably encounters challenges in thermal dissipation since stacked dies generate a significant amount of heat per unit volume. We leverage an integrated design methodology of stacked-signal-TSVs to minimize temperature. Based on this structure, a three-stage TSV locating algorithm in global routing is designed. We demonstrate that our results, compared with baseline circuits, have 17% temperature reduction with 3% wiring overhead and no performance loss calculated by 3-D Elmore delay model. Compared with the paper by Cong and Zhang where additional thermal TSVs are inserted, our experimental results have in average 23% less TSVs with the same temperature constraint. Compared with the paper by Pathak and Lim, where movable signal TSVs are relocated to reduce temperature in hotspot regions, our result has 8% more temperature reduction with the same number of signal TSVs.

A PSO-based timing-driven Octilinear Steiner tree algorithm for VLSI routing considering bend reduction

Constructing a timing-driven Steiner tree is very important in VLSI performance-driven routing stage. Meanwhile, non-Manhattan architecture is supported by several manufacturing technologies and now well appreciated in the chip manufacturing circle. However, limited progress has been reported on the non-Manhattan performance-driven routing problem. In this paper, an efficient algorithm, namely, TOST_BR_MOPSO, is presented to construct the minimum-cost spanning tree with a minimum radius for performance-driven routing in Octilinear architecture (one type of the non-Manhattan architecture) based on multi-objective particle swarm optimization (MOPSO) and Elmore delay model. Edge transformation is employed in our algorithm to make the particles have the ability to achieve the optimal solution while Union-Find partition is used to prevent the generation of invalid solution. For the purpose of reducing the number of bends which is one of the key factors of chip manufacturability, we also present an edge-vertex encoding strategy combined with edge transformation. To our best knowledge, no approach has been proposed to optimize the number of bends in the process of constructing the non-Manhattan timing-driven Steiner tree. Moreover, the theorem of Markov chain is used to prove the global convergence of our proposed algorithm. Experimental results indicate that the proposed MOPSO is worthy of being studied in the field of multi-objective optimization problems, and our algorithm has a better tradeoff between the wire length and radius of the routing tree and has achieved a better delay value. Meanwhile, combining edge transformation with the encoding strategy, the proposed algorithm can significantly reduce nearly 20 % in the number of bends.

A NOVEL INTERCONNECT STRUCTURE FOR ELMORE DELAY MODEL WITH RESISTANCE-CAPACITANCE-CONDUCTANCE SCHEME

In this brief, we present a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects f or a lumped and distributed line. This proposed mod el introduces a simple tractable delay formula by inco rporating conductance (G) into Resistance, Capacita nce (RC) network by preserving the characteristics of t he Elmore delay model. The RCG model attains quick steady state condition and the accuracy of the inte rconnect delay estimates can be improved by deployi ng the conductance effect. The simulation results show s the proposed interconnect scheme performance is better than the existing in terms of delay, power a nd the figure of merit. The performance analysis de picts that the proposed scheme has improved its figure of merit with minimum and maximum of 21.12% and 49.13%. The analysis is validated through extensive simulations on a 250 nm CMOS technology.

Electrical Network Functions of Common-Ground Uniform PassiveRLCLadders and Their Elmore’s Delay and Rise Times

In the paper are presented the expressions for all network functions of common-ground, uniform passive ladders having, in general, complex terminations at both their ends. The Elmore's delay and rise times calculated for selected types ofRLCladders have indicated their slight deviation from delay and rise times obtained according to their classical definitions. For common-ground, integrating typeRCladder with voltage-step input, the Elmore's delay- and rise-times are produced in closed-form, both for ladder nodes and points. Furthermore, it is proposed a particular common-ground, uniformRLCladder being amenable to application as delay line for pulsed and analog input signals. For this ladder, the Elmore's delay and rise times relating to their node voltages are produced in a closed-form, enabling thus with the realization of artificial (a) pulse delay line with arbitrarily and independently specified overall Elmore's delay and rise times and (b) true delay line with arbitrarily specified delay time for frequency bounded analog and/or pulsed input signals. In cases (a) and (b), precise procedures are formulated for calculation of ladder length and of all itsRLCparameters. The obtained results are illustrated with several practical examples and are, also, verified throughpspicesimulation.

Gate sizing using geometric programming

A two-step transistor sizing optimization method based on geometric programming for delay/area minimization is presented. In the first step, Elmore delay is minimized using only minimum and maximum transistor size constraints. In the second step, the minimized delay found in the previous step is used as a constraint for area minimization. In this way, our method can target simultaneously both delay and area reduction. Moreover, by relaxing the minimized delay, one may further reduce area with small delay penalty. Gate sizing may be accomplished through transistor sizing tying each transistor inside a cell to a same scale factor. This reduces the solution space, but also improves runtime as less variables are necessary. To analyze this tradeoff between execution time and solution quality a comparison between gate sizing and transistor sizing is presented. In order to qualify our approach, the ISCAS’85 benchmark circuits are mapped to a 45 nm technology using a typical standard cell library. Gate sizing and transistor sizing are performed considering delay minimization. Gate sizing is able to reduce delay in 21 %, on average, for the same area and power values of the sizing provided by standard-cells library. Then, the transistor sizing is executed and delay can be reduced in 40.4 % and power consumption in 2.9 %, on average, compared to gate sizing. However, the transistor sizing takes about 23 times longer to be computed, on average, using a number of variables twice higher than gate sizing. Gate sizing optimizing area is executed considering a delay constraint. Three delay constraints are considered, the minimum delay given by delay optimization and delay 1 and 5 % higher than minimum delay. An energy/delay gain (EDG) metric is used to quantify the most efficient tradeoff. Considering the minimum delay, area (power) is reduced in 28.2 %, on average. Relaxing delay by just 1 %, area (power) is reduced in 41.7 % and the EDG metric is 41.7. Area can be reduced in 51 %, on average, relaxing delay by 5 % and EDG metric is 10.2.

Delay Estimation for Global RC Interconnect UsingInverse Gamma Distribution Function

In this paper, we present an efficient model for on- chip interconnects delay analysis. Several approaches have already been proposed for approximating the interconnect delay accurately and efficiently. Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (the first moment of the impulse response) expression to the moment matching methods which create reduced order trans-impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an accurate approach for fitting moments of the impulse response to probability density functions so that delay can be estimated accurately at an early physical design stage. For RC trees, it is demonstrated that inverse gamma functions provide a probably stable approximation. The accuracy of the proposed model is justified with the results obtained from that of SPICE simulations.

Improving Elmore Model of RLC Networks for Applying to SWCNT Interconnects

Elmore delay has been widely used as an analytical estimate of the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. In this paper, Closed-form solutions for the 50% delay, rise time and overshoots of the step response of distributed Single Wall Carbon Nanotube (SWCNT), which consists RC and RLC parts, are presented for the first time. The proposed approach retains both efficiency and simplicity of the equivalent Elmore model with significantly improved accuracy, through surface fitting (3D) instead of curve fitting (2D).

Fast Waveform Estimation (FWE) for Timing Analysis

This paper proposes a new technique, fast waveform estimation (FWE), to quickly and accurately estimate the output waveform for general resistance-capacitance (RC) interconnect networks in the presence of coupling noise. It is a common view that the traditional transient analysis is not feasible for full-chip timing analysis. The static methods suffer from inaccuracy and inability to capture the non-monotonic nature of signal waveform in the presence of coupling noise. The dynamic methods, such as, general model order reduction techniques provide a good compromise between the accuracy and efficiency. But they make no use of the typical topological structures of the general RC interconnect networks. The proposed FWE technique achieves a better overall performance through topological reduction of the general RC interconnect networks. It is demonstrated that the accuracy of the proposed method is comparable to the general model order reduction-based methods while maintaining an efficiency that is comparable to Elmore delay based analysis.

Closed form Delay Model for on-Chip VLSIRLCG Interconnects for Ramp Input for Different Damping Conditions

Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Several approaches have been put forward which consider the inductance for on-chip interconnect modelling. But for even much higher frequency, of the order of few GHz, the shunt dielectric lossy component has become comparable to that of other electrical parameters for high speed VLSI design. In order to cope up with this effect, on-chip interconnect has to be modelled as distributed RLCG line. Elmore delay based methods, although efficient, cannot accurately estimate the delay for RLCG interconnect line. In this paper, an accurate analytical delay model has been derived, based on first and second moments of RLCG interconnection lines. The proposed model considers both the effect of inductance and conductance matrices. We have performed the simulation in 0.18μm technology node and an error of as low as less as 5% has been achieved with the proposed model when compared to SPICE. The importance of the conductance matrices in interconnect modelling has also been discussed and it is shown that if G is neglected for interconnect line modelling, then it will result an delay error of as high as 6% when compared to SPICE.