A NOVEL INTERCONNECT STRUCTURE FOR ELMORE DELAY MODEL WITH RESISTANCE-CAPACITANCE-CONDUCTANCE SCHEME

Ramadass Ramadass

doi:10.3844/ajassp.2013.881.892

Abstract

In this brief, we present a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects f or a lumped and distributed line. This proposed mod el introduces a simple tractable delay formula by inco rporating conductance (G) into Resistance, Capacita nce (RC) network by preserving the characteristics of t he Elmore delay model. The RCG model attains quick steady state condition and the accuracy of the inte rconnect delay estimates can be improved by deployi ng the conductance effect. The simulation results show s the proposed interconnect scheme performance is better than the existing in terms of delay, power a nd the figure of merit. The performance analysis de picts that the proposed scheme has improved its figure of merit with minimum and maximum of 21.12% and 49.13%. The analysis is validated through extensive simulations on a 250 nm CMOS technology.

Highlights

Increasing demand in circuit compaction, speed and high level of integration entail an accurate interconnect models to verify the performance and functionality of Very Large Scale Integration (VLSI) circuits
We present a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects for a lumped and distributed line
The performance analysis depicts that the proposed scheme has improved its figure of merit with minimum and maximum of 21.12% and 49.13%

Summary

Introduction

Increasing demand in circuit compaction, speed and high level of integration entail an accurate interconnect models to verify the performance and functionality of VLSI circuits. The main limitation to this model is inaccurate and the analysis is limited to estimate the delay of the circuit for the first order moments These classical problems has been surrogated through compound interest problem to the existing Elmore delay to improve the efficiency of the RC interconnect scheme. The modified Elmore delay model through compund interest has been reported by (Avci and Yamacli, 2010) Albeit this scheme improves accuracy but the estimation is restricted for RC network alone. Mal and Dhar (2010) has reported a dominant pole delay model by fixing the resistance and capacitance value for estimating the delay of arbitary RC network. This model provides delay accuracy to the first order RC network

Methods

Results

Discussion

Conclusion