Elliptic Curve Cryptography Processor Research Articles

Secured V2X communication using optimized prime field ECC architecture

The objective of this research is to ensure a high level of security in various forms of vehicular communication (V2V, V2I, and V2N) and to support vehicles in safely receiving all keys and messages from Roadside Unit (RSU), other vehicles, or the network with the support of simple cryptographic techniques. Elliptic Curve Cryptography (ECC) is one of the many cryptographic techniques that offer a desirable response to this requirement. The Koblitz curve secp256k1 is supported by the designed ECC processor for 256-bit point multiplication and point addition. A powerful illustration of the "Divide and Conquer" strategy's ability to accelerate multiplication asymptotically is given by the Karatsuba algorithm. The ECC processor's multiplication operation is accelerated further by the incorporation of pipelining. With a maximum clock frequency of 238.40MHz, the proposed Karatsuba-based ECC processor executes 256-bit single point multiplication in 0.937ms, providing 273.21kbps throughput, and taking up 8.42k slices in a Virtex-7 FPGA. Scalar multiplication is extended by incorporating a pipeline by increasing the highest clock frequency by up to 7.97%, which decreases time consumption by 9.90% and boosts throughput by 10.99%. In terms of area, operating frequency, area-delay product, and throughput, the suggested pipelined Karatsuba multiplier based ECC processor performs better than the existing designs.

An efficient implementation of Hybrid Signcryption Processor using Flexible Encryption and Signature Techniques

In today’s digital era, with the enormous growth in the Internet of Things, everyday humans utilize IoT in various applications such as banking, online transactions, purchasing data forwarding, etc. Cryptography is all about the design and implementation of protocols that keep the data safe and secure from third parties. The design of the cryptographic processor present in the Field Programmable Gate Array (FPGA) incurs more power, area, and throughput. In this article, an Efficient Hybrid Signcryption Processor (EHSP) which operates based on the principle of encryption and signature is proposed. Generally, a hybrid signcryption operation comprises of Data Encapsulation Method (DEM) and Key Encapsulation Method (KEM). and in EHSP, we utilize the improved form of the Modified Kurosawa and Desmedt (MKD) hash scheme to encapsulate the key; the Elliptic Curve Cryptography (ECC) processor is used to encapsulate the message. The ECC processor is designed in a flexible manner and the flexibility is achieved by the flexible bit-serial multiplier, which reduces the power, and area consumption and maximizes the throughput. The proposed EHSP architecture is designed and simulated in Xilinx tool with various field programmable gate array families such as Virtex4 (XC4VLX60), Virtex5 (XC5VLX50), and Virtex7 (XC7V330T). The simulation result depicts the efficiency of the proposed EHSP design with respect to total power consumption, utilization of hardware, and throughput.

Large Field-Size Elliptic Curve Processor for Area-Constrained Applications

This article has proposed an efficient area-optimized elliptic curve cryptographic processor architecture over GF(2409) and GF(2571). The proposed architecture employs Lopez-Dahab projective point arithmetic operations. To do this, a hybrid Karatsuba multiplier of 4-split polynomials is proposed. The proposed multiplier uses general Karatsuba and traditional schoolbook multiplication approaches. Moreover, the multiplier resources are reused to implement the modular squares and addition chains of the Itoh-Tsujii algorithm for inverse computations. The reuse of resources reduces the overall area requirements. The implementation is performed in Verilog (HDL). The achieved results are provided on Xilinx Virtex 7 device. In addition, the performance of the proposed design is evaluated on ASIC 65 nm process technology. Consequently, a figure-of-merit is constructed to compare the FPGA and ASIC implementations. An exhaustive comparison to existing designs in the literature shows that the proposed architecture utilizes less area. Therefore, the proposed design is the right choice for area-constrained cryptographic applications.

Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor

With the rising data evolution, the demand for secured communications over networks is rising immensely. Elliptic Curve Cryptography (ECC) provides an attractive solution to fulfill the requirements of modern network applications. Many proposals published over the year over different variants of ECC satisfied some of the issues. Nevertheless, modern network applications such as Internet-of-Thing (IoT) and Software-Defined Networking (SDN) put the requirements on various aspects and can only be solved by different ECC algorithms. Looking at this point of view, an efficient architecture that could combine multiple ECC algorithms becomes an urgent request. In addition, even though many investigations of ECC on Field-Programmable Gate Arrays (FPGA), an efficient architecture that could be well-deployed on Application-Specific Integrated Circuit (ASIC) needs to get more study. Therefore, this paper proposes an area-efficient ECC hardware design that could integrate multiple ECC algorithms. The proposed design is deployed on both ASIC and FPGA platforms. Four well-known ECC-based Digital Signature Algorithms (DSAs), which are the Edwards-curve Digital Signature Algorithm (EdDSA) with Curve25519, Elliptic Curve Digital Signature Algorithm (ECDSA) with National Institute of Standards and Technology (NIST) Curve P-256, P-384, and P-521, are implemented. Furthermore, the design supports all DSA schemes: public-key generation, signature generation, and verification. We also provide optimized calculation flows for modular multiplication, modular inversion, point addition, point doubling, and Elliptic Curve Point Multiplication (ECPM) for two different elliptic curves: the NIST curve and Edward curve, on a unique architecture. The calculation processes are designed in projective coordinates and optimized in time and space to achieve a high level of parallelism. The proposed ECC processor could run up to 102-MHz on ASIC 180-nm and 109.7-MHz on Xilinx Virtex-7. In terms of area, The processor occupies 377,471 gates with 4.87- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$mm^{2}$ </tex-math></inline-formula> on the ASIC platform and 11,401 slices on the FPGA platform. The experimental results show that our combinational design achieves area-efficient even when compared with other single-functional architecture on both ASIC and FPGA.

EC-Crypto: Highly Efficient Area-Delay Optimized Elliptic Curve Cryptography Processor

EC-Crypto: Highly Efficient Area-Delay Optimized Elliptic Curve Cryptography Processor

A Dual-Core High-Performance Processor for Elliptic Curve Cryptography in GF(p) Over Generic Weierstrass Curves

A dual-core high-performance processor for Elliptic Curve Cryptography (ECC) in GF( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> ) over Generic Weierstrass Curves was presented in this brief. Firstly, an optimized radix-128 Montgomery modular multiplication algorithm was proposed. It takes 6 clock cycles to calculate modular multiplication, which promotes the speed of elliptic curve point-addition (PA) and elliptic curve point-doubling (PD). Secondly, a dual-core hardware architecture which includes PD core and PA core to calculate elliptic curve point-multiplication (PM) was developed. It can speed up the PM by adopting parallelism with different levels and optimizing the scheduling. Finally, a data transfer architecture between PA and PD cores was proposed which requires only a 1024-bit register. It improves the speed of PM. The proposed design consumes 996k gates and compute the PM in 0.017 ms on ASIC with a 90 nm standard cell library. Moreover, the proposed design is also implemented on FPGA (Virtex-6 platform), which consumes 182k LUTs and compute the PM in 0.056 ms.

Programmable implementation of time-area-efficient Elliptic Curve Cryptography for entity authentication

In the ever increasing wireless reliant technologies, communications and devices, the demand for effective security with low hardware and high speed is wanting in the cryptography domain. Among the various cryptographic algorithms, the Elliptic Curve Cryptography (ECC) provides an attractive solution for this demand. In this paper, the Remote Keyless system Authentication process using the ECC has been implemented in Field Programmable Gate Array (FPGA). The designed ECC processor supports 256-bit point multiplication and point addition on the Koblitz curve secp256k1. The scalar multiplication has been performed with the faster multiplier Urdhva Tiryagbhyam. Additionally, pipelining has been incorporated in order to speed up the multiplication process of the processor. The proposed ECC processor performs single point multiplication of 256-bit in 1.2062ms with a maximum clock frequency of 192.5MHz, which provides 212.23kbps throughput and occupies 8.23k slices in Virtex-7 FPGA. Incorporating pipeline in scalar multiplication improves the maximum clock frequency up to 15.12%, reduces time consumption by 22.36%, which in turn increases the throughput by 22.36%. The proposed pipelined Vedic multiplier based ECC processor outperforms the existing designs in terms of area, operating frequency, area-delay product and throughput. Hence, the implementation of the proposed method offers time-area-efficient fast scalar multiplication with effective hardware utilization without any compromise in security level.

Implementation and Performance Analysis of Elliptic Curve Cryptography using an Efficient Multiplier

In Elliptic Curve Cryptography (ECC), modular multiplication in a finite field is a resource-consuming operation. The design of an efficient multiplier for ECC implementation in FPGA is an ever-evolving research problem. In this paper, we provide an efficient implementation of ECC for GF (2<SUP>233</SUP>) in FPGA. We propose a hybrid Karatsuba multiplier which is found to be occupying lesser slices compared to other optimized Karatsuba multiplier in [1]. This, in turn, amends the efficiency of the ECC processor in the FPGA platform. The proposed processor is implemented in ZedBoard containing Xilinx XC7Z020-1CLG484C Zynq-7000 AP SoC. In comparison with other similar works, the implementation results of ECC show consequential competitiveness in hardware efficiency and we obtain an efficient multiplier and ECC processor realized in FPGA. From the application point of view, ZedBoard has an ARM Processor and hence this can be utilized in vehicle On-Board Units (OBU) because of its lightweight properties.

A high speed processor for elliptic curve cryptography over NIST prime field

Elliptic curve cryptography (ECC), as one of the public key cryptography systems, has been widely applied to many security applications. It is challenging to implement a scalar multiplication (SM) operation which has the highest computational complexity in ECC. In this study, we propose a hardware processor which achieves high speed and high security for ECC. We first present a three-clock cycle, divide-and-conquer multiplication algorithm which greatly reduces the number of execution cycles of multiplication. We then propose a dedicated multiplication hardware structure which reuses the multiplier and optimizes data path delay. To keep multiplication running in non-idle status and executing in parallel with other modular operations, the operation scheduling of point addition and point doubling has been re-designed and optimized based on an effective segmentation and pipeline strategy. Finally, under the premise of similar computing and hardware overhead, we propose an improved high-security SM algorithm which involves random points to resist side-channel attacks. On a 55 nm complementary metal oxide semiconductor application specific integrated circuit platform, the processor costs 463k gates and requires 0.028 ms for one SM. Our results indicate that the ECC processor is superior to other state-of-the-art designs reported in the literature in terms of speed and area-time product metrics.

A High-Performance ECC Processor Over Curve448 Based on a Novel Variant of the Karatsuba Formula for Asymmetric Digit Multiplier

In this paper, we present a high-performance architecture for elliptic curve cryptography (ECC) over Curve448, which to the best of our knowledge, is the fastest implementation of ECC point multiplication over Curve448 to date. Firstly, we introduce a novel variant of the Karatsuba formula for asymmetric digit multiplier, suitable for typical DSP primitive with asymmetric input. It reduces the number of required DSPs compared to previous work and preserves the performance via full parallelization and pipelining. We then construct a 244-bit pipelined multiplier and interleaved fast reduction algorithm, yielding a total of 12 stages of pipelined modular multiplication with four stages of input delay. Additionally, we present an efficient Montgomery ladder scheduling with no additional register is required. The implementation on the Xilinx 7-series FPGA: Virtex-7, Kintex-7, Artix-7, and Zynq 7020 yields execution times of 0.12, 0.13, 0.24, and 0.24 ms, respectively. It increases the throughput by 242% compared to the best previous work on Zynq 7020 and by 858% compared to the best previous work on Virtex-7. Furthermore, the proposed architecture optimizes nearly 63% efficiency improvement in terms of Area&#x00D7;Time tradeoff. Lastly, we extend our architecture with well-known side-channel protections such as scalar blinding, base-point randomization, and continuous randomization.

High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field Along with RSA Comparison

Creating a high-speed elliptic curve cryptographic (ECC) processor capable of performing fast point Multiplication with low hardware utilisation is a critical requirement in cryptography and network security. This paper describes the implementation of a high-speed, field-programmable gate array (FPGA) in this paper. A high-security digital signature technique is implemented using Edwards25519, a recently approved twisted Edwards’s curve. For point addition and point doubling operations on the twisted Edwards curve, advanced hardware configurations are developed in which each task involves only 516 and 1029 clock cycles, respectively. As an observation the ECC processor presented in this paper begins with the process which takes 1.48 ms of single-point multiplication to be performed. The comparison of key size and its ratio which shows the impact on processing of each processor is shown for ECC processor and RSA processor. The delay and number of slices used for the ECC processor is shown and this is a developed solution saves time by providing rapid scalar multiplication with low hardware consumption without compromising on security.

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA.

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over , which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

High Performance and Low Latency ECC Processor for Cryptography

Elliptic curve cryptography processor implemented for point multiplication on field programmable gate array. Segmented pipelined full-precision multiplier is used to reduce the latency and also data dependency can be avoided by modifying Lopez-Dahab Montgomery PM Algorithm, results in drastic reduction in the number of clock cycles required. The proposed ECC processor is implemented on Xilinx FPGA families i.e. virtex-4, vitrtex-5, virtex-7.single and three multiplier based designs show the fastest performance compared with reported work individually. Our three multiplier based ECC processor implementation is taking the lowest number of clock cycles on FPGA based design processor.

A High-Speed Elliptic Curve Cryptography Processor for Teleoperated Systems Security

Teleoperated robotic systems are those in which human operators control remote robots through a communication network. The deployment and integration of teleoperated robot’s systems in the medical operation have been hampered by many issues, such as safety concerns. Elliptic curve cryptography (ECC), an asymmetric cryptographic algorithm, is widely applied to practical applications because its far significantly reduced key length has the same level of security as RSA. The efficiency of ECC on GF (p) is dictated by two critical factors, namely, modular multiplication (MM) and point multiplication (PM) scheduling. In this paper, the high-performance ECC architecture of SM2 is presented. MM is composed of multiplication and modular reduction (MR) in the prime field. A two-stage modular reduction (TSMR) algorithm in the SCA-256 prime field is introduced to achieve low latency, which avoids more iterative subtraction operations than traditional algorithms. To cut down the run time, a schedule is put forward when exploiting the parallelism of multiplication and MR inside PM. Synthesized with a 0.13 um CMOS standard cell library, the proposed processor consumes 341.98k gate areas, and each PM takes 0.092 ms.

Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve

With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications

This brief presents an energy-efficient elliptic curve cryptography (ECC) processor for Internet of Things (IoT) security applications. The proposed processor supports dual-field computations, and employs various design techniques across the algorithm, architecture, and arithmetic circuit levels to minimize power and energy consumption. The proposed elliptic curve point multiplication (ECPM) algorithm employs signed binary representation (SBR) with the m-ary method to reduce both area and energy consumption, while avoiding attack from simple power analysis (SPA). In addition, the proposed hybrid modular arithmetic architecture effectively increases the hardware utilization to reduce both area and energy cost. Finally, the proposed processor uses an energy-efficient data flow to further minimize memory overhead for group operations. The proposed ECC processor achieves 51.6% and 50.5% lower energy consumption for each GF(p) and GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) ECPM operation, respectively, when compared to state-of-the-art ECC designs.

LUT‐based high‐speed point multiplier for Goldilocks‐Curve448

Recent studies have shown that existing elliptic curve-based cryptographic standards provide backdoors for manipulation and hence compromise the security. In this regard, two new elliptic curves known as Curve448 and Curve25519 are recently recommended by IETF for transport layer security future generations. Hence, cryptosystems built over these elliptic curves are expected to play a vital role in the near future for secure communications. A high-speed elliptic curve cryptographic processor (ECCP) for the Curve448 is proposed in this study. The area of the ECCP is optimised by performing different modular operations required for the elliptic curve Diffie–Hellman protocol through a unified architecture. The critical path delay of the proposed ECCP is optimised by adopting the redundant-signed-digit technique for arithmetic operations. The segmentation approach is introduced to reduce the required number of clock cycles for the ECCP. The proposed ECCP is developed using look-up-tables (LUTs) only, and hence it can be ported to any field-programmable gate array family or standard ASIC libraries. The authors' ECCP design offers higher speed without any significant area overhead to recent designs reported in the literature.

An efficient hardware implementation of the elliptic curve cryptographic processor over prime field,

SummaryElliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest‐Shamir‐Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, . This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex‐7 FPGA platform over 224‐bit and 256‐bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal‐oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field and , respectively. This design provides better area‐delay product and high throughput value in both FPGA and ASIC when compared with other designs.

Adapted Semi Carry Save Modular Montgomery Multiplier for High-Performance Elliptic Curve Cryptographic Processor

Adapted Semi Carry Save Modular Montgomery Multiplier for High-Performance Elliptic Curve Cryptographic Processor

Redundant-Signed-Digit-Based High Speed Elliptic Curve Cryptographic Processor

In this paper, a high speed elliptic curve cryptographic (ECC) processor for National Institute of Standards and Technology (NIST) recommended prime [Formula: see text] is proposed. The modular arithmetic components in the proposed ECC processor are highly optimized at both architectural level and circuit level. Redundant-signed-digit (RSD) arithmetic is adopted in the modular arithmetic components to avoid lengthy carry propagation delay. A high speed modular multiplier is designed based on an efficient segmentation and pipelining strategy. The clock cycle count is reduced as result of the segmentation, whereas operating frequency and throughput are significantly increased due to the pipelining. An optimized pipelined architecture for modular division is also presented which is suitable for the design of ECC processor using projective coordinates. The Joye’s double and add (DAA) algorithm based on [Formula: see text]-only common [Formula: see text] (co-[Formula: see text]) coordinate is adopted at the system level for its regular and efficient behavior. The proposed ECC processor is flexible and can be implemented using any field programmable gate array (FPGA) family or standard cell libraries. The proposed ECC processor executes a single elliptic curve (EC) point multiplication (PM) operation in 0.47[Formula: see text]ms at a maximum frequency of 327[Formula: see text]MHz on Virtex-6 FPGA. The implementation results demonstrate that the proposed ECC processor outperforms the other contemporary designs reported in the literature in terms of speed and [Formula: see text] metrics.