Implementation and Performance Analysis of Elliptic Curve Cryptography using an Efficient Multiplier

Abstract

In Elliptic Curve Cryptography (ECC), modular multiplication in a finite field is a resource-consuming operation. The design of an efficient multiplier for ECC implementation in FPGA is an ever-evolving research problem. In this paper, we provide an efficient implementation of ECC for GF (2<SUP>233</SUP>) in FPGA. We propose a hybrid Karatsuba multiplier which is found to be occupying lesser slices compared to other optimized Karatsuba multiplier in [1]. This, in turn, amends the efficiency of the ECC processor in the FPGA platform. The proposed processor is implemented in ZedBoard containing Xilinx XC7Z020-1CLG484C Zynq-7000 AP SoC. In comparison with other similar works, the implementation results of ECC show consequential competitiveness in hardware efficiency and we obtain an efficient multiplier and ECC processor realized in FPGA. From the application point of view, ZedBoard has an ARM Processor and hence this can be utilized in vehicle On-Board Units (OBU) because of its lightweight properties.