Logic Elements Research Articles

Chaos blended cellular automata on fractals: the effective way of reconfigurable hardware assisted medical image privacy.

In more recent times data continues to be generated at a very unprecedented scale. This is a result of the pervasive nature of modern-day digitisation. As such, it is absolutely critical that this data only be accessed by the trusted parties concerned in an effort to maintain the privacy of individuals. One particular type data that could severely compromise the identity and privacy of an individual is ‘medical data’. With a focus on medical images, this work proposes a novel ‘fractalized’ chaos-cellular automata encryption scheme, implemented on Cyclone IV EP2C35F672C6 FPGA, resulting in a hardware-based concurrent security solution. The scheme entails three stages of diffusion, which arise from different mechanisms. In tandem with the diffusion process is the “On the Fly” process of confusion governed by a Linear feedback Shift Register (LFSR), all of which in implemented by applying the nature of fractals. The security architecture occupies 16,351 Logic Elements (LEs) with 230 registers on the target FPGA with the power dissipation of 133.39 mW. Further, the encryption achieves near zero correlation with the average entropy of 15.17156 that ensures the statistical properties. In addition, the security framework requires 12.13 ms to encrypt a 256 × 256 × 16 DICOM image which results in the throughput of 86.44 Mbps. The proposed encryption resists the brute force attack and chosen plain text attack by achieving a very large span of keyspace.

Electronically Reconfigurable Photonic Switches Incorporating Plasmonic Structures and Phase Change Materials.

The ever‐increasing demands for data processing and storage will require seamless monolithic co‐integration of electronics and photonics. Phase‐change materials are uniquely suited to fulfill this function due to their dual electro‐optical sensitivity, nonvolatile retention properties, and fast switching dynamics. The extreme size disparity however between CMOS electronics and dielectric photonics inhibits the realization of efficient and compact electrically driven photonic switches, logic and routing elements. Here, the authors achieve an important milestone in harmonizing the two domains by demonstrating an electrically reconfigurable, ultra‐compact and nonvolatile memory that is optically accessible. The platform relies on localized heat, generated within a plasmonic structure; this uniquely allows for both optical and electrical readout signals to be interlocked with the material state of the PCM while still ensuring that the writing operation is electrically decoupled. Importantly, by miniaturization and effective thermal engineering, the authors achieve unprecedented energy efficiency, opening up a path towards low‐energy optoelectronic hardware for neuromorphic and in‐memory computing.

Combined ground-fault relay protection in 6–10 kV power grids

In the present work, engineering decisions for combined ground-fault relay protection in 6–10 kV power grids are addressed. For objects in electrical grids having a voltage of 6–10 kV, simple relay protection was used: overcurrent protection and current cutoff. The most common algorithms for single phase-to-earth fault relay protection were analysed and compared. The modelling allowed a scheme for automatic transfer switch to be designed. Operation algorithms of relay protection and automatics were established, considering the properties of an electrical grids section and the characteristics of possible operating conditions. In 6–10 kV electrical grids, an increase in the damage rate of cable lines with outdated thinned insulation was revealed. It was determined that long-term grid operation under a single phase-to-earth fault should be avoided since double earth faults may occur due to an increase in the voltage of healthy phases relative to earth by √3 times. The calculations performed to evaluate selectivity and sensitivity of the current protection of selective zero-sequence showed limited application (due to the insufficient sensitivity) of such protection from single phase-to-earth fault in some cases. The advantages of circuit designs, which use electromagnetic and inductive relays as protection fault detectors, and advanced compact elements in the form of microcircuits with electronic interconnection as logical elements, were investigated. It is established that the proposed solutions can be used by energy providers to increase the reliability and fail-safety of 6–10 kV distribution networks with the minimum capital expenditures to relaying systems. The presented analysis of systems and devices for phase-to-earth fault relay protection showed that power grids having isolated neutrals are the most problematic in terms of maintenance. Simplified circuit designs for combined protection circuits can be used for facilitating the maintenance of relaying devices and automatics due to their openness.

Low power residue number system using lookup table decomposition and finite state machine based post computation

In this paper, memory optimization and architectural level modifications are introduced for realizing the low power <span lang="EN-US">residue number system (RNS) with improved flexibility for electroencephalograph (EEG) signal classification. The proposed RNS framework is intended to maximize the reconfigurability of RNS for high-performance finite impulse response (FIR) filter design. By replacing the existing power-hungry RAM-based reverse conversion model with a highly decomposed lookup table (LUT) model which can produce the results without using any post accumulation process. The reverse conversion block is modified with an appropriate functional unit to accommodate FIR convolution results. The proposed approach is established to develop and execute pre-calculated inverters for various module sets. Therefore, the proposed LUT-decomposition with RNS multiplication-based post-accumulation technology provides a high-performance FIR filter architecture that allows different frequency response configuration elements. Experimental results shows the superior performance of decomposing LUT-based direct reverse conversion over other existing reverse conversion techniques adopted for energy-efficient RNS FIR implementations. When compared with the conventional RNS FIR design with the proposed FSM based decomposed RNS FIR, the logic elements (LEs) were reduced by 4.57%, the frequency component is increased by 31.79%, number of LUTs is reduced by 42.85%, and the power dissipation was reduced by 13.83%.</span>

Flexible Ionic Diodes with High Rectifying Ratio and Wide Temperature Tolerance

AbstractSoft iontronics expand the toolbox of bio‐integrated or bio‐interfaced devices, owing to their natural resemblance with living systems; however, the development for analogous integrated ionic circuits is immature due to the difficulty of fabricating fundamental ionic logic elements. Among these, ionic diodes have motivated great endeavors for their unique ionic current rectifying characteristics. Nonetheless, it is still challenging to achieve high‐performance ionic diodes; also, most reported aqueous solution‐based ionic diodes fail to work at extreme temperatures, seriously hindering their practical uses. This work reports a highly rectifying, temperature‐tolerant, and flexible hydrogel ionic diode enabled by an ethylene glycol/water binary solvent system. The ionic diodes exhibit outstanding dehydration resistance to high temperatures (100 °C) and anti‐freezing performance at low temperatures (−20 °C). Rectification ratios as high as 1201 (with 0% ethylene glycol content) and 566 (with 40% EG content) are achieved, which are distinctly advantageous over most previous reports. A flexible four‐diode bridge full‐wave rectifier circuit is then fabricated, and its integration with the triboelectric nanogenerator for effective biomechanical energy harvesting is demonstrated. This work is believed to open up new insights for the development of future bio‐interfaced applications.

Cotranscriptionally encoded RNA strand displacement circuits.

Engineered molecular circuits that process information in biological systems could address emerging human health and biomanufacturing needs. However, such circuits can be difficult to rationally design and scale. DNA-based strand displacement reactions have demonstrated the largest and most computationally powerful molecular circuits to date but are limited in biological systems due to the difficulty in genetically encoding components. Here, we develop scalable cotranscriptionally encoded RNA strand displacement (ctRSD) circuits that are rationally programmed via base pairing interactions. ctRSD circuits address the limitations of DNA-based strand displacement circuits by isothermally producing circuit components via transcription. We demonstrate circuit programmability in vitro by implementing logic and amplification elements, as well as multilayer cascades. Furthermore, we show that circuit kinetics are accurately predicted by a simple model of coupled transcription and strand displacement, enabling model-driven design. We envision ctRSD circuits will enable the rational design of powerful molecular circuits that operate in biological systems, including living cells.

Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model

Approximate computing is an upsurging technique to accelerate the process through less computational effort while keeping admissible accuracy of error-tolerant applications such as multimedia and deep learning. Inheritance properties of the deep learning process aid the designer to abridge the circuitry and also to increase the computation speed at the cost of the accuracy of results. High computational complexity and low-power requirement of portable devices in the dark silicon era sought suitable alternate for Complementary Metal Oxide Semiconductor (CMOS) technology. Gate Diffusion Input (GDI) logic is one of the prompting alternatives to CMOS logic to reduce transistors and low-power design. In this work, a novel energy and area efficient 1-bit GDI-based full swing Energy and Area efficient Full Adder (EAFA) with minimum error distance is proposed. The proposed architecture was constructed to mitigate the cascaded effect problem in GDI-based circuits. It is proved by extending the proposed 1-bit GDI-based adder for different 16-bit Energy and Area Efficient High-Speed Error-Tolerant Adders (EAHSETA) segmented as accurate and inaccurate adder circuits. The proposed adder's design metrics in terms of delay, area, and power dissipation are verified through simulation using the Cadence tool. The proposed logic is deployed to accelerate the convolution process in the Low-Weight Digit Detector neural network for real-time handwritten digit classification application as a case study in the Intel Cyclone IV Field Programmable Gate Array (FPGA). The results confirm that our proposed EAHSETA occupies fewer logic elements and improves operation speed with the speed-up factor of 1.29 than other similar techniques while producing 95% of classification accuracy.

All-Optical Parallel Programmable Logic Element Based on Binary Decision Diagram Mapping in Micro-Ring Resonators

All-Optical Parallel Programmable Logic Element Based on Binary Decision Diagram Mapping in Micro-Ring Resonators

Implementation of Simplified Data Encryption Standard on FPGA using VHDL

In recent years, dramatic changed has been made in communication sector. Due to enormous development in communication devices, globally internet-connected network largely used in all human activities. The security of information has been becoming a major concern for all users and clients, whom depend on network system. The cryptography has played significant role to combat these challenges and improve confidentiality, integrity, and authentication of data communication in the network. The Data Encryption Standard (DES) is one of most familiar type of cryptography and widely used in the modern network system, which has been adopted in encryption and decryption a digital information for several decades. The DES is replaced by a number of new cryptographical methods, which based on DES, like AES and 3DES. In the same time some hardware tools have gained a lot of attention and become interested for researchers and academics to design and implement their model proposals with these hardware-based tools. Therefore, this paper, shows the design of a Simplified Data Encryption Standard (S-DES) by using VHDL language. The design is synthesized, compiled and implemented on the FPGA Altera board, which, consists Quartus II software environment, and Altera Cyclone IV 4CX150FPGA device. The S-DES has been successfully implemented with few numbers of logic elements.

Information system for ontological modelling the subject areas

Objectives. The creation of ontologies of subject areas is considered. The goal is to develop a mathematical model of ontology and the information system for ontological modeling. The task is to reduce the complexity of ontological modeling.Methods. As research methods, the theory of hybrid intelligence systems, the theory of sets, elements of mathematical logic, methods for developing the information systems, comparative analysis of information systems, informal analysis of information system were used.Results. Mathematical model of ontology using the concept of metaobject is developed. Ontological modelling based on this model involves specification, conceptualization and formalization. A glossary of terms is being built at the specification stage. At the conceptualization stage, objects in the subject area and their hierarchy are defined, and then connections between objects are identified. In the formalization stage, the metaobjects and the relationships between metaobjects that correspond to objects and the relationships between objects were defined. This is considered as the ontology of the subject area. During the actualization stage, the parameters of subject area objects and their values, classes, subclasses, and instances of classes were defined. Parameters, parameter values, classes, subclasses, and instances of classes are implemented in ontology as metaobjects of relative types. An information system with a unique architecture has been developed, namely a hybrid intelligence system for the automation of ontological modelling.Conclusion. The article conducts a comparative analysis of the developed information system with the systems used today for creation of ontologies. The analysis showed that the information system developed by paper author in most parameters is not inferior to considered systems and at the same time easier to use and expand. The mathematical model of ontology and the information system for ontological modeling of subject areas, developed by author, are tested in practical creation of ontology on ecology. On the basis of the conducted comparative analysis and informal analysis of practical use, it is concluded that ontological modeling with the help of the information system developed by author reduces the labor intensity and decreases the time of ontologies creation.

Blockchain-Enabled Supply-Chain in Crop Production Framework

Abstract The purpose of this paper is to propose an approach to blockchain-enabled supply-chain model for a smart crop production framework. The defined tasks are: (1) analysis of blockchain ecosystem as a network of stakeholders and as an infrastructure of technical and logical elements; (2) definition of a supply-chain model; (3) design of blockchain reference infrastructure; (4) description of blockchain information channels with smart contracts basic functionalities. The results presented include: а supply-chain model facilitating seeds certification process, monitoring and supervision of the grain process, provenance and as optional interactions with regulatory bodies, logistics and financial services; the three level blockchain reference infrastructure and a blockchain-enabled supply-chain supporting five information channels with nine participants and smart contracts. An account management user application tool, the general descriptions of smart contract basic functionalities and a selected parts of one smart contract code are provided as examples.

Physically unclonable functions with controlled propagation delay

O b j e c t i v e s. The problem of constructing a new class of physically uncloneable functions (PUF) based on controlling the signal propagation delay through the elements lying on the path of its propagation is being solved. The relevance of this problem is associated with the active development of physical cryptography. For its implementation, the following goals are pursued: the construction of the basic elements of the PUF and their modifications, the development of a methodology for constructing controlled ring oscillators based on XOR elements and controlled ring oscillators based on multi-input signal switching.M e t h o d s. Methods of synthesis and analysis of digital devices were used, including those based on programmable logic integrated circuits (FPGA), the basics of Boolean algebra and circuitry.R e s u l t s. It is shown that combined PUFs based on RS-flip-flops implement the idea of controlling the signal delay by choosing a path, which is a series-connected elements selected in accordance with the PUF request. A technique for constructing an PUF with a controlled delay through each element of the path has been developed as a development of the idea of controlling the signal delay along the path. The features and properties of PUF with controlled delay of signals of the ring oscillator type are investigated and possible solutions are shown for the case of two-bit input requests. A basic element and its modifications are proposed for constructing new PUF structures based on the control of the signal propagation delay. It is shown that the signal delay through the basic element, which is a multi-input XOR element, depends not only on the number of inputs to which the active input signal is applied, but also on fixed values of 0 or 1 at its other inputs. A new PUF structure is presented, namely, a controlled ring oscillator, its implementation is considered for the case of control by setting the inputs and their number, by which the active input signal changes.Co n c l u s i o n. The proposed new approach to the construction of physically uncloneable functions, based on the control of signal delay through logical elements, has shown its efficiency and promise. The effect of the influence on the delays of signal propagation through the logic element, both the number of its inputs, along which the input signals change, leading to a change in the output signal, and their composition, is experimentally confirmed. It seems promising to further developing the ideas of constructing controlled ring oscillators and oscillators with multi-input switching of input signal, as well as the creation of new PUF structures of arbiter type.

On elementary logics for quantitative dependencies

We define and study logics in the framework of probabilistic team semantics and over metafinite structures. Our work is paralleled by the recent development of novel axiomatizable and tractable logics in team semantics that are closed under the Boolean negation. Our logics employ new probabilistic atoms that resemble so-called extended atoms from the team semantics literature. We also define counterparts of our logics over metafinite structures and show that all of our logics can be translated into functional fixed point logic implying a polynomial time upper bound for data complexity with respect to BSS-computations.

Demonstration of reconfigurable magnetic tunnel diode and giant tunnel magnetoresistance in magnetic tunnel junctions made with spin gapless semiconductor and half-metallic Heusler alloy

Here, we report fabrication of a high quality exchanged biased trilayer magnetic tunnel junction (MTJ) utilizing a magnetron sputtering system. The MTJ is composed of a type-II spin gapless semiconductor (SGS) Ti2CoSi inverse Heusler alloy (used as a lower electrode), a thin MgO layer (used as a tunnel barrier), and a half-metallic ferromagnet (HMF) Co2MnSi Heusler alloy (used as an upper electrode). Spin dependent transport properties reveal that the micro-fabricated MTJ can act as a reconfigurable magnetic tunnel diode, which lets the electric current to flow in either the forward or reverse path relying on the relative alignment of the magnetization direction of the upper and lower magnetic electrodes. A considerably high on/off current ratio (∼103) and a significantly low turn on voltage (VT) of 0.09 V have been achieved at 5 K for both parallel and antiparallel configurations. Another important characteristic shown by our fabricated MTJ is that it exhibits extremely large tunnel magnetoresistance ratios of 892% at 5 K and 197% at room temperature, which brings to light the utmost importance of using the combination of HMF and SGS materials as magnetic electrodes in a tunnel junction for potential applications in modern spintronic devices. All these exceptional features can undoubtedly nominate CMS/MgO/TCS MTJs as a promising candidate to serve as memory or logic elements in next generation ultra-high density magnetoresistive random access memories together with contemporary spin based electronic devices.

Optically initialized and current-controlled logical element based on antiferromagnetic-heavy metal heterostructures for neuromorphic computing

A concept of optically triggered and electrically controlled ultra-fast neuromorphic computing processor based on an antiferromagnetic/heavy metal (AFM/HM) heterostructure is proposed. The AFM/HM-based artificial neurons are excited with short THz-range pulses, triggering precession in AFM. Bias electric current in the HM layer can be used to modify the resonance frequency of precession. The conversion of the precession into the electric current in the HM-layer occurs via the inverse spin Hall effect. A model of a neuromorphic processor is, thus, proposed, consisting of excitatory AFM-based artificial neurons—oscillators, and processing neurons—detectors. We show that the use of optical excitation can significantly increase the processing speed of neuromorphic computing at low power consumption. Examples of the implementation of the simplest logical operations (OR, AND) are demonstrated.

Interaction-free bidirectional multi-channel all-optical switching in a multi-level coupling atom-cavity system.

We propose a scheme of interaction-free bidirectional multi-channel all-optical switching in a multi-level coupling system consisting of four-level atoms confined in a cavity and coupled by a free-space control laser. A signal laser field is coupled into the cavity and excites two separate transitions of atoms simultaneously under the collective strong coupling condition. The transmission and reflection of signal fields form bidirectional output channels. A free-space control laser induces destructive quantum interference in the multi-level excitation of an atom-cavity system, which can be used to switch on/off the output signal lights of transmission/reflection channels. There is no direct coupling of control light and signal light through the cavity-confined atoms because the output of signal light is nearly totally suppressed to the opposite direction when control light is present. The proposed all-optical switching scheme can be realized with high switching efficiency, broad bandwidth, and weak light intensity. It may be useful for future devices of optical routing, optical communications, and various quantum logic elements.

Information decision-making support for periodic maintenance of gas balloon equipment

The issues of information support for decision-making during periodic maintenance of gas-cylinder equipment of vehicles running on natural gas, ensuring safe operation, contributing to an increase in the efficiency of transportation of goods and goods: reducing vehicle downtime due to failure of the fuel system using gas fuel by 10–18%; reducing the likelihood of functioning of gas equipment in hazardous modes by 12–17%. The technical requirements for gas equipment and procedures for its periodic maintenance are formulated. The concept of the formation and application of a unified state register of gas equipment, which is a tool for limiting admission to the turnover of products that does not meet regulatory and market requirements, is proposed. An information-logical model of decision-making support has been developed, which allows, depending on the current technical condition of assemblies and parts, based on the specified requirements for the duration of the period between maintenance, to propose the best option for carrying out diagnostic, repair and commissioning measures for gas-cylinder equipment of vehicles. The procedure for the formation of an extended list of measures for periodic maintenance of gas equipment is presented on the example of individual nodes of the fuel system of a vehicle running on compressed natural gas. The software implementation of the information- logical model is carried out in the form of a plug-in extension to the database core of the decision support information system for the operation of gas equipment, implemented on the Oracle database management system with integrated support for the high-level object- oriented language Java. For the convenience of working with the information-logical model, a computational and analytical module of the information system for decision-making support during the operation of gas-cylinder equipment with elements of fuzzy logic has been developed. The model was tested on the example of the implementation of measures during the periodic maintenance of the gas equipment of the KamAZ 65116 truck.

Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model.

Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.

Реализация оптимального построения комбинационного устройства и оценка надёжности по выходному напряжению

The theoretical propositions of the algebra of logic are considered. It is noted that the current microcircuitry based on the algebra of logic contains logical statements: true (yes) is a logical unit, false (no) is a logical zero. Based on the given logical function: ((ABC)×D + A×(BCD) + A×(BC)×D + (AB)×(CD), frontal, minimal, transformed minimal variants of the combination device are implemented, as well as minimized variants in the bases "AND-NOT" and "OR-NOT". A combination device based on import-substituting chips of 155, 176 series has been designed. The analysis of the obtained devices is made from the standpoint of technical and economic indicators, in particular, an assessment of the number of logic elements used, an assessment of the symmetry of the structure, as a result, a reduction in energy consumption, an increase in performance, improvements in parameters for reliability of functioning, a decrease in weight and size characteristics. Assuming that the law of change of the information parameter U1 is close to linear, taking into account the effect of temperature as boundary values for the elements of the applied microcircuits, taking the values -60 °C and +120°. Accordingly, the parametric reliability of the optimal implementation of the device according to the output voltage parameter is calculated. The conclusion is made about the inverse dependence of parametric reliability on temperature growth. A recommendation is given when evaluating parametric reliability for a number of other information parameters about the need to take into account both the number of chips used and the type of their interconnections.

Two-layer logic elements for classic cryogenic computers

In this paper, for the first time, two-layer logic elements "NOT", "AND", "OR" and "NOR" were manufactured, in which the heating element of a nanowire in one layer is located in the place where the heated element of another superconductive nanowire is located in a nearest NbN layer. The film thickness of NbN (5-7 nm) was used to form of superconducting nanowires in different layers, and the thickness of Al2O3 (25 nm) was used as an interlayer dielectric. The paper shows the design of logic elements, and also demonstrates their operation in pulse mode. The use of multilayer structures without galvanic coupling between nanowires allows the design of multi-level logic devices. Keywords: NbN thin superconducting films, contactless switching of the superconductor state, cryoelectronic devices, integrated cryogenic resistors, logic elements "NOT"/"AND"/"OR"/"NOR", cryogenic computers.