Electrostatic Discharge Protection Devices Research Articles

Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip

The dual-directional silicon-controlled rectifier (DDSCR) is an electrostatic discharge (ESD) protection device. It can provide positive and negative ESD surge paths and has excellent robustness. However, industry-level sensors operating in strong electromagnetic interference environments impose higher reliability requirements on photoelectric chips. This paper proposed a novel DDSCR with a dual-gate controlled mechanism. By incorporating the gate diode triggering and the gate field modulation mechanism into the traditional DDSCR, and further utilizing additional parasitic bipolar junction transistors (BJTs) for diversion, the proposed device exhibits significantly improved ESD characteristics. Measurement results indicate that, compared to DDSCR, the proposed device exhibits a 27.5% reduction in trigger voltage (Vt1 ), a 96.1% improvement in holding voltage (Vh ), and achieves an equivalent human body model protection level of 11.45 kV, demonstrating exceptional design area efficiency. The experimental findings validate the effectiveness of the proposed device in 5 V photoelectric chip applications.

Design and verification of a hybrid electrostatic discharge model for Gate-Controlled silicon controlled rectifier

The DC breakdown characteristic of electrostatic discharge (ESD) protection device, which is an important indicator of its transparency and circuit compatibility, has received widespread attention. Currently, methods such as Verilog-A hardware description language, circuit-level SPICE simulation, and process-level device modeling cannot simultaneously achieve high accuracy, good convergence, and fast simulation speed. Therefore, in this paper, a hybrid ESD model based on Technology Computer Aided Design (TCAD) device-level simulation, Monte Carlo numerical modeling and Verilog-A behavioral modeling is proposed to characterize the ESD characteristics of gate-controlled silicon-controlled rectifier (GCSCR). A device-level model of GCSCR was established using TCAD, and the working mechanism was simulated. By extracting the electric field from TCAD and using the Monte Carlo modeling method, the DC characteristic of GCSCR was accurately characterized. In addition, the snapback characteristic of the device was successfully simulated by Verilog-A. The effectiveness of the above approaches was further verified based on the 0.18 μm standard BCD (Bipolar-CMOS-DMOS) process. Comparison results indicate that the hybrid model exhibits high simulation accuracy, good convergence and good universality and scalability, providing a simple and effective modeling solution for ESD devices of different structures and sizes.1This work is supported by the National Natural Science Foundation of China (Grant No. 62174052, 61827812), Hunan Science and Technology Department Huxiang High-level Talent Gathering Project (Grant No. 2019RS1037) and Innovation Project of Science and Technology Department of Hunan Province (Grant No. 2020GK2018).

ESD Research of SCR Devices under Harsh Environments.

In prior technology, system-level electrostatic discharge (ESD) tests under environment change conditions mainly focused on testing the effect of a high-temperature environment. i.e., the effect on internal circuits of heat generated outside. However, few studies have explored the effect of ambient relative humidity changes on integrated circuits (ICs). Therefore, this study will analyze the performance of various ESD protection components under high ambient temperature and high ambient relative humidity. The ESD protection devices are tested for the ESD robustness of the silicon-controlled rectifiers (SCR) under a harsh environment and the measurement results are discussed and verified in the CMOS process.

Graphene-Based ESD Protection for Future ICs.

On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection.

A high performance RC-INV triggering SCR under 0.25 µm process

PurposeAs it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time.Design/methodology/approachBased on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness.FindingsThe RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+.Originality/valueUnder 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.

Optimization on Bi-Directional PNP ESD Protection Device for High-Voltage FlexRay Applications

The I/O of CMOS integrated circuits of for FlexRay communication has to be tolerant with the input signals of ±60 V in its normal applications. Thus, the on-chip electrostatic discharge (ESD) protection devices for such I/O pin must be kept off unless the bus voltage is higher than 60 V or lower than −60 V. In this work, the bi-directional p-n-p (Bi-PNP) device was proposed and optimized for bi-directional ESD protection in the FlexRay communication systems. The proposed Bi-PNP devices were verified in a 0.15- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD technology. The relationships between the layout spacing of doping layers and other device characteristics, including trigger voltage (Vt1) and breakdown voltage (BV), were investigated, respectively. The size dependence on the ESD robustness was also studied. The transient response of the proposed Bi-PNP device under fast ESD stress was investigated by very fast TLP (vf-TLP) and TLP measurement. In addition, the empirical correlations of the It2 on the HBM and IEC 61000-4-2 failure levels were estimated. Finally, the recommended size and parameters of the proposed Bi-PNP device for ±60 V FlexRay application are provided.

Design of capacitor-less LDO regulator with SCR-based ESD protection using dual push-pull stage

ABSTRACT The external capacitors of conventional LDO (Low Drop Out) regulator have a function to improve the transient response characteristics affected by the overshoot and undershoot. However, the LDO regulator proposed in this study is replaced the function of the external output capacitor with a dual push-pull stage and is achieved a fast transient response by a newly added control path to replace the function of the capacitor removed along with the existing feedback path. The proposed LDO regulator can also be provided the improved ESD (Electro Static Discharge) robustness characteristics by applying the SCR (Silicon Control Rectifier)-based ESD (Electro Static Discharge) protection device embedded into the output node and power line. The LDO regulator with dual push-pull circuit proposed in this study was operated at a maximum load current of 100 mA, an output voltage of 3 V, and an input voltage range of 3.3 ~ 4.5 V. As a result of the measurement, an undershoot voltage of 110 mV and an overshoot voltage of 123 mV were maintained when a load current of 100 mA was applied. Further, the ESD robustness characteristic of HBM is guaranteed at 8kV or higher.

Transient Response of ESD Protection Devices for a High-Speed I/O Interface

System-efficient electrostatic discharge (ESD) design (SEED) models of a diode and transient voltage suppressor (TVS) were developed to study their transient response in a high-speed input/output interface. Previously reported SEED models were improved to strengthen their convergence stability and facilitate accurate predictions over a wide range of conditions. These improvements were required to accurately capture the race conditions between the TVS and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip diode, where the diode's turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> may prevent turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> of the TVS. Simulations and measurements were performed to demonstrate the impact of the ESD pulse's rise time on race conditions. During a race, results showed the worst-case quasi-static diode current could be twice as high for long rise-time pulses than for short rise-times where the TVS does not turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> , and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip diode current may be larger at low test voltages than at high test voltages where the TVS does turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> . Adding a small passive impedance between the external TVS and the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip diode helps the TVS turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and reduce the current through the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip diode by more than 50%. Similarly, lengthening the trace between the TVS and diode could reduce <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip diode current by up to a factor of two.

Optimizing the on-chip electrostatic discharge protection device by Taguchi's methodology

The study presents the use of Taguchi method to obtain the best ESD performance devices and compares the performance with other methods. A full-factor method to obtain the best ESD performance devices can achieve all experimental factor effects, but at a significant cost. Through silicon data validation and analysis, Taguchi's method has been shown to save two-thirds of the cost for optimal ESD devices compared to the full-factor approach. In addition, if the layout area is very concerned in advanced technologies such as 40 nm and 28 nm, a tentative method called the single-factor-middle-level method is proposed as another ESD device optimization method.

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

A novel structure of low-voltage trigger silicon-controlled rectifiers (LVTSCRs) with low trigger voltage and high holding voltage is proposed for electrostatic discharge (ESD) protection. The proposed ESD protection device possesses an ESD implant and a floating structure. This improvement enhances the current discharge capability of the gate-grounded NMOS and weakens the current gain of the silicon-controlled rectifier current path. According to the simulation results, the proposed device retains a low trigger voltage characteristic of LVTSCRs and simultaneously increases the holding voltage to 5.53 V, providing an effective way to meet the ESD protection requirement of the 5 V CMOS process.

A Millimeter-Wave Broadband Reflectionless ESD Protection Device

In this letter, a broadband millimeter-wave (mm-wave) electrostatic discharge (ESD) protection structure is proposed and verified in a 40-nm CMOS process. The main ESD protection device is a diode-triggered silicon-controlled rectifier (DTSCR) with a tunable trigger voltage. Two weakly-coupled inductors are embedded to increase the operating bandwidth. Both theoretical analysis and simulation results show that a low coupling factor is necessary to obtain the wideband characteristic. The proposed design exhibits good ESD protection performance (HBM robustness >1.875kV), fast turn-on speed, wideband reflectionless characteristic (S11<–15dB within 33.6-50GHz), tunable trigger voltage and low leakage current. Therefore, this new device is suitable for ESD protection of input/output (I/O) pads in mm-wave-communication applications.

Frequency Based Method Investigation to Extract an ESD Protection Dynamic SPICE Model From TLP Measurement

In order to ensure reliability of systems early in the design phase, it is becoming crucial to have models able to predict the behaviors of systems exposed to electrostatic discharge (ESD). This is an increased necessity since the number of embedded electronic products is growing and since they are involved in applications where people&#x0027;s safety is a requirement. Until now, quasi-static models of protection devices have succeeded in providing fairly good results in failure predictions (mainly hard failures). Today, the increased frequency range of the devices requires dynamic models able to reproduce its transient behavior. In this article, we investigate if conventional modeling methods of linear devices, generally used in frequency domain, could be used to get an equivalent frequency model for ESD protection devices, which exhibit a nonlinear behavior. A methodology to extract an ESD protection SPICE model from transmission line pulse (TLP) measurements to address transient and frequency simulation is proposed and detailed. We will demonstrate that in well-defined conditions, such frequency models can give accurate results to predict overshoots related to protection devices triggering delays. Validation of the models is performed under TLP and human metal model conditions on three off-the-shelf devices.

Study on the high-temperature triggering and holding characteristics of PDSOI SCR devices

In this paper, the triggering and holding characteristics of electrostatic discharge (ESD) protection devices operating under various ambient temperatures ranging from 25 °C to 300 °C are investigated. The measured ESD protection devices were silicon-controlled rectifier (SCR) devices fabricated in 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. Measurements were conducted using the transmission line pulse (TLP) test system. The triggering voltage, VT1, and the holding voltage, VH, of the SCR devices show negative coefficient phenomenon with the increasing temperature. The similarities and differences between the triggering condition and the holding condition are analyzed in detail. The underlying physical mechanisms related to the effects of temperature on the VT1 and VH are provided by the assist of technology computer-aided design (TCAD) simulation.

Analyzing the impact of guard-ring on different dual-direction SCR by device simulation and TLP measurement

In this paper, the impact of the traditional interdigital DDSCR structure (TI-DDSCR) and the embedded DDSCR (EM-DDSCR) structure with and without P+ guard-ring is analyzed under the 0.5-μm complementary and double-diffused MOSFET (CDMOS) technology. In order to verify and predict the characteristics of those electrostatic discharge (ESD) protection devices, a transmission line pulse (TLP) testing system and device simulation platform have been used in this work. The test results show that the introduction of P + guard ring will increase the device forward trigger voltage (Vt1) by about 3 V and forward holding voltage (Vh) by 4-6 V, but has little effect on the forward failure current (It2). The reverse Vh is reduced by 4–6 V, while the reverse It2 depends on the layout geometry. Due to the different layout geometry, on the TI-DDSCR structure with P+ guard ring, their reverse It2 is reduced from 13.07A to 8.05A. On the contrary, on the EM-DDSCR with P+ guard ring, their reverse It2 increased from 6.55A to 10.10A.

System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure.

3-D TCAD Methodology for Simulating Double-Hysteresis Filamentary I–V Behavior and Holding Current in ESD Protection SCRs

Current filament (CF)-related double-hysteresis I-V behavior and holding current, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD</sub> ,are analyzed using experiments and 3-D technology computer-aided design (TCAD) simulation in silicon-controlled rectifiers (SCR) for system-level electrostatic discharge (ESD) protection. Our 3-D TCAD methodology uses up and down quasi-dc current sweeps to reveal a memory effect in the current density distribution along the device width. I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> is related to the smallest possible CF where the self-sustaining SCR action takes place during down current sweep. I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD</sub> exhibits a nontrivial dependence on device width, depending on whether a CF is created or not. Analyzing devices of different layouts shows that I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> values determined from experiments and 3-D TCAD are almost layout-independent and substantially lower than those evaluated from 2-D TCAD. I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> calculated by 3-D TCAD in edge-terminated devices is higher than that in 3-D structures obtained from simple width-extended 2-D doping profiles. The use of latter devices, thus, simplifies the 3-D TCAD I- V analysis and provides a safe margin for I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> prediction. The work is relevant for designing the latch-up immunity of ESD protection devices, and it also shows that conventional 2-D TCAD can provide unwanted overestimation of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD</sub> .

Design of a Robust ESD Protection Device using 6H-SiC Nano-Scale GGNMOS

With the continuous shrinking of the technological nodes and the introduction of new device concepts and materials, integrated circuits (IC) are becoming more vulnerable to electrostatic discharge (ESD) induced failures which is one of the major concerns in designing robust ICs.  Therefore, to improve the reliability of the ICs against ESD induced failures, extensive research efforts are being conducted. In this paper, we have presented a 6H-SiC based nano-scale grounded-gate NMOS (ggNMOS) ESD protection device and compared the results with the 3C-SiC-based ggNMOS. To design a robust ESD protection device, some critical device parameters, such as substrate doping concentration, source/drain doping concentration, drain to substrate contact spacing, and substrate contact resistance should be optimized. The ESD protection characteristics can be improved by utilizing the near punch-through effect. It was found that the trigger voltage and hold voltage are higher in 6H-SiC than the 3C-SiC having identical device parameters. 6H-SiC shows better voltage clamping performance as the turn-on resistance of 6H-SiC is smaller compared to the 3C-SiC material. Therefore, the results show that 6H-SiC has a better performance compared to 3C-SiC and due to its higher bandgap, and can be used as a good ESD protection device. All the simulations are carried out using the Silvaco ATLAS device simulator.

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

Rapid characterization of efficient system level ESD protection strategy using coupling transfer function

This study details a new technique for the fast and efficient design and analysis of system level electrostatic discharge (ESD) protection strategy using developed coupling transfer impedance function. The transfer coupling characteristics from the zapping point to the victim location on a DUT can be computed using coupling transfer gain function. Subsequently, it is integrated with an ESD current source in a SPICE type circuit simulator for the fast and efficient analysis of induced ESD coupling noise and the design of the appropriate ESD protection scheme with the suitable choice of ESD protection device (diodes, SCR, GGNMOS, GCNMOS etc.). The study discusses the different protection schemes i.e. primary, secondary and double ESD protections, and the effect of the selected diode types and ESD stressing levels on the employed protection strategy. The proof-of-concept is validated through the rapid design of suitable system level ESD protection strategy for a microstrip-line PCB, high-speed mobile device memory module, and a portable notebook motherboard.

Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures* *Project supported by the National Natural Science Foundation of China (Grant No. 61804168).

Trigger characteristics of electrostatic discharge (ESD) protecting devices operating under various ambient temperatures ranging from 30 °C to 195 °C are investigated. The studied ESD protecting devices are the H-gate NMOS transistors fabricated witha 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. The measurements are conducted by using a transmission line pulse (TLP) test system. The different temperature-dependent trigger characteristics of grounded-gate (GGNMOS) mode and the gate-triggered (GTNMOS) mode are analyzed in detail. The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V T1 are investigated through the assist of technology computer-aided design (TCAD) simulation.