Optimizing the on-chip electrostatic discharge protection device by Taguchi's methodology

Abstract

The study presents the use of Taguchi method to obtain the best ESD performance devices and compares the performance with other methods. A full-factor method to obtain the best ESD performance devices can achieve all experimental factor effects, but at a significant cost. Through silicon data validation and analysis, Taguchi's method has been shown to save two-thirds of the cost for optimal ESD devices compared to the full-factor approach. In addition, if the layout area is very concerned in advanced technologies such as 40 nm and 28 nm, a tentative method called the single-factor-middle-level method is proposed as another ESD device optimization method.