Electrostatic Discharge Protection Circuit Research Articles

ESD protection under grounded-up bond pads in 0.13 μm eight-level copper metal, fluorinated silicate glass low-k intermetal dielectric CMOS process technology

Electrostatic discharge (ESD) protection device under the grounded-up bond pad is investigated in 0.13 /spl mu/m full eight-level copper metal CMOS process technology with fluorinated silicate glass (FSG) low-k intermetal dielectric (IMD), The bonding force and power produces no cracking and no noticeable change in the second breakdown trigger point (V/sub t2/) I/sub t2/). High current I-V measured from the different level metal layer stack structures shows that 1) I/sub t2/ depends very weakly on metal layers used, as expected due to certain junction power dissipation criterion and 2) V/sub t2/ increases with the number of metal layers, The origin of the latter is increased dynamic impedance for increased metal layer number, as clarified by a simple RC model. The model also yields the intrinsic second breakdown trigger current and voltage for the underlying ESD protection device, Successfully configuring ESD protection circuits under the bond pads, therefore, not only is wholly free from the traditional area consumption, but also can substantially relax design constraints, enabling much more flexible and robust ESD schemes for various applications,.

Silicon controlled recitfiers type electrostatic discharge protection circuits with variable holding voltage

A new design of silicon controlled recitfiers (SCR)-type electrostatic-discharge (ESD) protection circuit has been presented. In the design we vary the number of stacked diodes in series with the npn transistor in the SCR to control the holding voltage. Experimental and analysis of the transient and steady-state I– V characteristics of SCR-type ESD protection circuits with variable holding voltage have been carried out. It has been experimentally verified that the holding voltage of SCR can be increased by increasing the number of stacked diodes and it can be designed to avoid accidential latchup caused by system overshooting.

TLP measurements for verification of ESD protection device response

This paper describes a simplified, yet general, TLP circuit and method called time domain transmission (TDT) mode testing. The TDT method differs from and is compared to time domain reflection (TDR) mode testing. Transmission line pulsers (TLPs) have been used for many years to calibrate diagnostics and provide precise high-voltage, high-current waveforms. The pulsers have been used to qualify the electrostatic discharge (ESD) response of ESD protection circuits and devices. TLP applications cover a wider range of uses beyond estimating the ESD susceptibility of device level protection circuits. TLPs have been used to certify many ESD suppression devices including: device level ESD protection circuits, metal oxide varistors (MOV), transorbs, composite voltage variable materials (VVM), diodes, spark gaps, and occasionally, even capacitors and resistors.

An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology

A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) protection circuit is designed to protect integrated circuits (ICs) against ESD surges in two opposite directions. The compact ESD protection circuit features low triggering voltage (/spl sim/7.5 V), short response time (0.18-0.4 ns), symmetric deep-snap-back I-V characteristics, and low on-resistance (/spl sim//spl Omega/). It passed the 14-kV human body model (HBM) ESD test and is very area efficient (/spl sim/80 V//spl mu/m width). The new ESD protection design is particularly suitable for low-voltage or multiple-power-supply IC chips.

ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications

An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins: for high-frequency or current-mode applications, By including an efficient power-rails clamp circuit in the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (/spl mu/m//spl mu/m) in a 0.35-/spl mu/m silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only /spl sim/1.0 pF (including the bond-pad capacitance) for high-frequency applications.

A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit.

Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology

The effect of scaling on electrostatic discharge (ESD) robustness in 1.2 to 0.25 μm channel length CMOS technologies is explored for ESD protection circuits and MOSFET structures. Results show that ESD robustness decreases as ESD structures are scaled to smaller dimensions in future technologies. Technology benchmarking, using a standardized ESD design, for evaluating ESD robustness is discussed. The ESD sensitivity of ESD designs to geometrical and semiconductor process parameters are evaluated. An analytical development for electro-thermal failure is developed based on electro quasi-static and adiabatic assumptions. ESD scaling relationships are developed applying MOSFET constant electric field scaling theory. ESD robustness scales as 1/α 3 2 , where α is the scaling parameter. The scaling relationship derived from the analytical model is then compared to established power-to-failure ESD models. The impact of MOSFET scaling on the ESD robustness of MOSFET structures is then discussed. MOSFET scaling as a function of technology generation shows that snapback breakover and sustaining voltages are decreasing with each technology generation. Optimization, design constraints and technology tradeoffs in CMOS technology development are then shown using a design curve methodology.

A study on the effect of the gate contact geometry and dimensions on ESD failure threshold level of power MOSFET's

The effect of the gate contact geometry and dimensions on the catastrophic electrostatic discharge (ESD) failure of power MOSFET's that have ESD protection circuits between their gate and source has been studied. This paper describes the relationship between the ESD failure threshold level and the gate contact width of MOSFET's. It has been found from numerical analysis that only the area near the gate contact, and not the entire gate, is sensitive to the ESD pulse, because the diffusion of the ESD charge into the inner region is suppressed by the sheet resistance of the gate polycrystalline silicon (poly-Si) film. It is also shown here that widening the gate contact and carefully designing the shape of the gate contact, as well as lowering the gate poly-Si sheet resistance, substantially enhance the ESD failure threshold level of power MOSFET's because a greater portion of an ESD charge can diffuse into the gate region of the device.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 mu /sup 2/, the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than +or-1 and +or-10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies. >

ESD in integrated circuits

A review of the effects of electrostatic discharge (ESD) on semiconductor integrated circuits is presented. The principles of the human body model (HBM), the machine model (MM) and the charged device model (CDM) test methods are outlined, and their relative merits and drawbacks are discussed. Techniques, such as the transmission line pulse method, which may be used to characterise ESD protection circuit elements are also presented. The concept of ESD protection circuit designs and some typical ESD protection circuit elements are presented. The main design and process parameters are identified, and the main categories of damage under ESD conditions are shown. Models of the behaviour of the protection circuit elements under high current conditions are presented, and the boundary conditions for damage are discussed. The issues that will influence ESD protection circuit behaviour in the future are discussed.

Optimized ESD protection circuits for high-speed MOS/VLSI

New electrostatic discharge (ESD) protection circuits for MOPS/VLSI provide typical 2.7-ns delays and protection against voltage spikes up to 2200 V (limit of test circuit) in some cases. These circuits contain some traditional elements plus new features including a gate-drain connected thin-oxide device to achieve the very low protected node voltage (~2 V) required for advanced thin gate oxide technologies. In addition, for CMOS application, these all-NMOS (or PMOS) circuits would offer a high degree of latchup immunity. For both positive and negative spikes, single-pulse and repeated-pulse test data were obtained for six different test conditions. Electrical and physical analyses show dominant failure modes. Because techniques used to improve protection tend to degrade speed, a figure of merit is proposed to assist a fair comparison between different ESD protection circuit designs.