Electrostatic Discharge Failure Voltage Research Articles

Research on ESD failure voltage model of the T-shaped wiring structure in GOA products

In the GOA (Gate on Array) circuits, which are commonly employed in LCD (Liquid Crystal Display) products, the metal wire layers have been found to be sensitive to ESD (Electrostatic Discharge) in production, leading to an increase in the failure rate of GOA products, especially in T-shaped wiring structures. In this paper, we conducted a study on the relationship between the ESD failure voltage and structure parameters of T-shaped wiring structures in GOA products to enhance their reliability. We established an ESD failure voltage model for T-shaped wiring structures based on the relevant electrical breakdown theory. And failure voltage and gap breakdown voltage data are required for accurate model parameters fitting. Hence, ESD tests on the T-shaped wiring structure samples were conducted. In addition, ESD simulation of T-shaped wiring structure using CST software was applied to supply gap voltage data unavailable from tests. Based on the results of the tests and simulation, parameters of the ESD failure voltage model were fitted. And we performed the model modification using verification tests for higher accuracy. The results show that our model errors are below 5 %. Guided by the ESD failure voltage model, a more reliable T-shaped structure can be produced in GOA.

Effect of Ground-Wall Structure in Capacitive Fingerprint Sensor on Electrostatic Discharge Tolerance

This paper describes the electrostatic discharge (ESD) tolerance of capacitive fingerprint sensor or sensor/identifier LSIs in which the sensor is stacked on a CMOS LSI. The ground-wall structure that we proposed as a capacitive sensor structure for ESD tolerance was investigated. The contact discharge method was used for the fingerprint sensor ESD test. The dependence of ESD failure voltage on the distance between the sensor surface and the ESD electrode was measured. In the planar-type structure, ESD failure voltage decreased as the electrode approached the sensor surface and reached its minimum when the electrode touched the surface. Results for the ground-wall type show a high ESD tolerance regardless of the distance. Moreover, in the test on the fingerprint sensor and sensor/identifier LSIs, the ground-wall effect was obtained with a high ESD tolerance. In conclusion, it was revealed that fingerprint sensor LSI or the fingerprint sensor/identifier LSI with a ground-wall structure has a high ESD tolerance of more than ±20.0 kV.

A study of an abnormal ESD failure mechanism and threshold voltage caused by ESD current zapping sequence

This paper presents a proposal on ESD (Electro Static Discharge) test method to understand an abnormal ESD failure caused by ESD current zapping sequence and to define an exact ESD threshold voltage. The abnormal ESD failure and threshold voltage level can not be detected by the prevailing used ESD test method which zapping ESD current stress to pins of DUT (Device Under Test) sequentially and automatically. Therefore this paper will show the abnormal ESD failure mechanismand also how to detect the actual ESD threshold voltage properly.

Electrostatic discharge testing of tunneling magnetoresistive (TMR) devices

We report on an experimental and SPICE simulation study of electrostatic discharge (ESD) damage of tunneling magnetoresistive (TMR) junctions. The human body model (HBM) ESD failure voltage was found to be 6 V/sub HBM/, higher than the 2 V DC breakdown voltage. This difference is explained in terms of the dependence of the HBM failure voltage on the resistance and capacitance of the TMR device. A simple SPICE model for a TMR device is used to study the response of a TMR device during an ESD event.

Novel concept for high level overdrive tolerance of GaAs based FETs

A novel FET concept, using low temperature grown GaAs as surface passivation and buffer layer material, has been developed to tolerate high levels of input overdrive and to improve electrostatic discharge (ESD) resistance. It is shown that high input levels 17 dB beyond the 1 dB compression point, do not lead to the burnout of the device and that, at the same time, the ESD failure voltage can be increased compared to conventional GaAs based MESFETs.

Improvements in electrostatic discharge performance of InGaAsP semiconductor lasers by facet passivation

Chemically treating laser facets with aqueous sulfides can significantly improve the electrostatic discharge (ESD) performance of InGaAsP semiconductor lasers. Commercial lasers free of internal defects were subjected to forward-biased Human Body Model ESD stress pulses. Devices passivated with sulfides exhibited a mean ESD failure voltage more than 400% higher than that of the untreated control group. Subsequent accelerated aging experiments suggest that a thick layer of oxide covering the laser facets, largely removed by the sulfide treatment, is responsible for the low ESD failure voltage on untreated devices. This suggests that sulfide passivation followed by facet encapsulation in a robust dielectric could result in permanent protection against ESD failure. >