Electrostatic Discharge Devices Research Articles

Risk assessment of fire and explosion accidents in oil-hydrogen fueling station based on fault tree analysis

Owing to the coexistence of gasoline, diesel, and hydrogen, a specific and thorough risk assessment approach must be promptly implemented for oil-hydrogen fueling stations. Consequently, this study makes innovations in considering the safety issues of the joint construction of gas station and hydrogen refueling station, and undertaking the modeling and analysis of fire and explosion incidents at oil-hydrogen fueling stations based on fault tree analysis. The findings reveal that the risk level for fire and explosion at oil-hydrogen fueling stations is categorized as grade III. In our fault tree analysis model, there are 3240 minimum cut sets and 194 minimum path sets. The probability of fire and explosion incidents occurring at oil-hydrogen fueling stations is calculated to be 0.000265. This indicates that while the possibility of such accidents is low, their potential severity is exceedingly high. Ultimately, it is recommended that the safety of oil-hydrogen fueling stations be enhanced through the reinforcement of emergency management, customer safety education, and electrostatic discharge devices.

Design and verification of a hybrid electrostatic discharge model for Gate-Controlled silicon controlled rectifier

The DC breakdown characteristic of electrostatic discharge (ESD) protection device, which is an important indicator of its transparency and circuit compatibility, has received widespread attention. Currently, methods such as Verilog-A hardware description language, circuit-level SPICE simulation, and process-level device modeling cannot simultaneously achieve high accuracy, good convergence, and fast simulation speed. Therefore, in this paper, a hybrid ESD model based on Technology Computer Aided Design (TCAD) device-level simulation, Monte Carlo numerical modeling and Verilog-A behavioral modeling is proposed to characterize the ESD characteristics of gate-controlled silicon-controlled rectifier (GCSCR). A device-level model of GCSCR was established using TCAD, and the working mechanism was simulated. By extracting the electric field from TCAD and using the Monte Carlo modeling method, the DC characteristic of GCSCR was accurately characterized. In addition, the snapback characteristic of the device was successfully simulated by Verilog-A. The effectiveness of the above approaches was further verified based on the 0.18 μm standard BCD (Bipolar-CMOS-DMOS) process. Comparison results indicate that the hybrid model exhibits high simulation accuracy, good convergence and good universality and scalability, providing a simple and effective modeling solution for ESD devices of different structures and sizes.1This work is supported by the National Natural Science Foundation of China (Grant No. 62174052, 61827812), Hunan Science and Technology Department Huxiang High-level Talent Gathering Project (Grant No. 2019RS1037) and Innovation Project of Science and Technology Department of Hunan Province (Grant No. 2020GK2018).

Novel ESD device design for STT-MRAM memory chip

An investigation of the influence of the magnetic field induced by electrostatic discharge (ESD) current on magnetic tunnel junction (MTJ) device is presented in the paper. The transient magnetic field generated by the ESD current is not considered in the traditional CMOS ESD protection strategy, which may be a reason of the degradation of the performance and the robustness of STT-MRAM. An ESD protection circuit of STT-MRAM is proposed in the paper, including the diode-based ESD devices, the filter circuit and the power clamp. Based on the waveform analysis of the three ESD standard test models, including HBM, MM and CDM, a filter circuit is added in the ESD device to decrease the influence of the high frequency components on the magnetic device. The diode-based ESD devices are integrated in the ESD structure, which is used for the ESD window of STT-MRAM for its low operating voltage. Based on the operation mechanism of the STT-MRAM, its ESD window allows a low operating voltage, thus the diode-based devices are chosen to be integrated in the ESD device. The distribution and magnitude of the magnetic field are studied in the paper. The results show that the ESD protection circuit of STT-MRAM can effectively suppress the magnetic field generated by the ESD current, hence increasing the stability of STT-MRAM. Under the influence of the HBM, MM and CDM events, the ESD disturbance probability of the MTJ device are 2.0 × 10−12, 5.8 × 10−9 and 1.1 × 10−12 respectively. The influence of the memory density and the distance between pads and memory array are also investigated in this paper. The ESD protection strategy proposed in the paper can be adopted for the future high performance STT-MRAM.

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

The holding voltage of electrostatic discharge (ESD) protecting structure is the critical parameter to determine the latch-up performance of the protecting device, but the thermal change of ESD device parameters lead the protecting device to suffer latch-up risk at high ambient temperature. In this paper, the holding characteristics of the ESD protecting device at various ambient temperatures ranging from 30 ℃ to 195 ℃ are studied. The investigated ESD structure is the N-channel metal oxide semiconductor (NMOS) transistors fabricated with the 0.18 μm partially depleted silicon-on-insulator process. The ESD characteristics of the device are measured by the transmission line pulse test system at different ambient temperatures. The test results show that the holding voltage (<i>V</i><sub>H</sub>) decreases with temperature increasing. The TCAD simulation is carried out to support and analyze the experimental results, and the same trend of <i>V</i><sub>H</sub> versus temperature is obtained. Through the analysis of simulation results and theoretical derivation, the underlying physical mechanisms related to the effects of temperature on <i>V</i><sub>H</sub> and holding current (<i>I</i><sub>H</sub>) are discussed in detail. When the drain is subjected to the same current pulsing and the Source and Body are both grounded, the distributions of current density, electric potential, and injected electron density of NMOS at various temperatures are extracted and analyzed. When the Drain, Source, and Body are all grounded, the distributions of the electrostatic field at various temperatures are extracted and analyzed. The distribution of electric potential in NMOS indicates that the voltage drop on the Drain-Body junction (<i>V</i><sub>DB</sub>) is affected by ambient temperature significantly, and the variation of <i>V</i><sub>DB</sub> dominates the variation trend of <i>V</i><sub>H</sub> with temperature increasing. The reducing electrostatic field and increasing injected electron density with temperature decreasing contribute to the decreasing of <i>V</i><sub>DB</sub>. The trend of <i>I</i><sub>H</sub> and parasitic Body resistance (<i>R</i><sub>Body</sub>) weakens the temperature dependence of the <i>V</i><sub>H</sub>. The current gain of parasitic bipolar transistor (<i>β</i>) decreases with ambient temperature rising, which is the main contributor to the decreasing of <i>I</i><sub>H</sub>. Therefore, increasing <i>I</i><sub>H</sub> and <i>R</i><sub>Body</sub> is helpful in reducing the temperature dependence of the latch-immune ESD protection structure.

Novel dual-direction electrostatic discharge device with lateral PNP transistor

With the shrinking of semiconductor technology and the increasing of integrated circuits, electrostatic discharge (ESD) as a common natural phenomenon has become one of the main reasons for the failure and reliability reduction of electronic products in integrated circuits. A novel dual-direction ESD device (PNP_DDSCR) with embedded lateral PNP transistor is proposed for diminishing ESD damage. The response process and current transportation of PNP_DDSCR under different ESD stress modes are investigated. Comparative analyses between conventional DDSCR and PNP_DDSCR are executed by TCAD simulation. On the stage of device triggering, the embedded lateral PNP transistor inner DDSCR system provides triggering current for device. The injection efficiency of parasitic transistor in the DDSCR system is improved, and the positive feedback system is promoted. Thus, the holding voltage of PNP_DDSCR is higher than that of conventional DDSCR. At the same time, an extra triggering path introduced by embedded lateral PNP transistor of PNP_DDSCR makes the total triggering path of device shorten. Therefore, the transient overshoot voltage of PNP_DDSCR is lower than that of DDSCR. For thermal performance, most of the heat first accumulates near the lateral PNP transistor , and then the peak point of heat turns to main SCR path with the conduction of PNP_DDSCR. The heat accumulation in PNP_DDSCR is shared by the path of embedded lateral PNP transistor. As a result, the average temperature in PNP_DDSCR is lower than that in DDSCR and the ability of PNP_DDSCR to dissipate heat is more perfect. Comparing with DDSCR, the conclusions are obtained. Under the condition of transmission line pulse (TLP) test simulation analyses, the triggering voltage is reduced by 31%, the holding voltage is increased by 16.8%, the ESD design window is optimized by 44.5%, and on-resistance is lower. When TLP stress is 2.67 A, the average temperature of PNP_DDSCR is much lower than that of traditional DDSCR in the whole conduction process. With the increase of pulse lasting time, average temperature difference between two devices becomes great further. According to the very fast TLP (VF-TLP) testing results, clamping capability of PNP_DDSCR under transient overshoot voltage is more stable under the condition of fast turn-on speed. When the VF-TLP stress is 0.1 A, the overshoot voltage of PNP_DDSCR device is the 37% of that of DDSCR device while the PNP_DDSCR maintains a relatively fast triggering speed. Thus, the ESD protection capability of PNP_DDSCR is superior.

Design and optimization of a gate-controlled dual direction electro-static discharge device for an industry-level fluorescent optical fiber temperature sensor

Design and optimization of a gate-controlled dual direction electro-static discharge device for an industry-level fluorescent optical fiber temperature sensor

A novel percolation model of leakage fluctuation behavior in gate-control dual-direction silicon controlled rectifier

Gate structures are used as efficient auxiliary components to improve the electrostatic discharge (ESD) performance of traditional silicon controlled rectifiers (SCRs). However, it has not been explored how the gate geometry potentially affects leakage behaviors and ESD characteristics of SCR devices. In this paper, a novel percolation model is proposed to address this problem. The percolation model fundamentally interprets the leakage fluctuation behavior of the gate-control dual-direction silicon controlled rectifier (GC-DDSCR) under ESD events. Two key parameters breakdown charge (QBD) and tunneling current (Jg) are simulated to link the gate geometry and gate oxide quality, revealing the principle of the leakage fluctuation behavior. The leakage fluctuation behavior may cause GC-DDSCR to work in an unstable state, leading to the premature functional failure of the intrinsic SCR path. Two GC-DDSCRs with different gate sizes are fabricated under a 0.5 μm CMOS technology and characterized by a transmission line pulse (TLP) test. Experiment results show the GC-DDSCR with a larger gate size is more prone to the leakage fluctuation behavior and the premature functional failure. The percolation model is qualitatively verified and the understanding of the gate structure in ESD devices is deepened.

Investigation of Different Conduction States on the Performance of NMOS-Based Power Clamp ESD Device

This article investigates the effects of different gate coupling voltage and gate voltage duration on electro-static discharge (ESD) performance of several NMOS-based power rail protection devices. Through simulation and transmission line pulse (TLP) test, it is found that there are two modes in the conduction process of the main clamping NMOS: channel conduction state and parasitic NPN conduction state. Different gate voltage and duration bring the two conduction states different proportions in the whole working process, which give the device very different robustness. The results show that under the condition of small gate voltage and long duration and the condition of large gate voltage and short duration, the device can achieve optimal performance because the trigger voltage can be reduced, and the parasitic NPN can be turned on in time to release most of the current.

Direct Visualization of Breakdown-Induced Metal Migration in Enhanced Modified Lateral Silicon-Controlled Rectifiers

The robustness of electrostatic sensitive devices is important in state-of-the-art silicon technology. However, the electrical breakdown-induced microstructure evolution remains unclear. In this work, we performed the physical failure analysis of breakdown in an enhanced modified lateral silicon-controlled rectifier-based electrostatic discharge (ESD) device. Direct visualization of the conductive metal filaments in the doped silicon substrate has been achieved by high-resolution transmission electron microscopy. The locations of these metal filaments induced by breakdown are found near the cathode. The evolution of these microstructural changes and chemical properties provides guide to the failure analysis of ESD devices.

Experimental results on diodes and BIMOS ESD devices in 28 nm FD-SOI under TLP & TID radiation

The electrostatic discharge (ESD) protection is a major concern for advanced CMOS technology manufacturing. Several solutions are available on market with efficient robustness and compliant with the ESD window especially in 28 nm FD-SOI technology. In the framework of harsh environment applications and to explore the performance under total ionizing dose (TID) radiation, it is important to investigate ESD protection devices such as gated and STI diodes in hybrid bulk or BIMOS solution in thin silicon film. This study is based on transmission line pulse (TLP) characterization before and after Co60 TID radiation in the range of [25 krad–200 krad]. This dose range is chosen for a first robustness exploration and in link with product applications. Following this analysis, we expect to gain better understanding of robustness and push the final performance of the device. The preliminary results will be useful to give a trend and to improve the device robustness against ESD and TID events and lead to more competitive solutions.

Design and analysis of a multi-finger dual-direction SCR discharging electro-static current in a gradual transition manner

In order to seek an electro-static discharge with higher failure current per unit area and latch-up immunity, a novel multi-finger dual-direction silicon controlled rectifier (DDSCR) using the 0.5 μm complementary and double-diffusion metal-oxide-semiconductor technology was proposed. The working principle of the device is analyzed by using equivalent circuit and technology computer aided design simulation. From the test result of the transmission line pulse testing system we can see that the holding voltages for the traditional dual-direction silicon controlled rectifiers with a single-finger and two-fingers are 11.34 V and 7.63 V, respectively, which is decreased as the number of fingers increases. The holding voltage of the proposed device is 12.2 V, which is higher than that of the traditional 2-finger DDSCR and suitable for communication interface high voltage electrostatic discharge (ESD) protection. Furthermore, the influence of some dimensions, fingers and total finger width on the device is discussed. The proposed device not only solves the problem of decreasing the holding voltage caused by increasing the number of fingers, but also has a slight effect on the failure current. The root cause for such holding voltage trend is their different working mechanisms. The proposed device is turning on one finger by another instead of simultaneously turning on in the multi-finger traditional devices. Therefore, the proposed ESD device owns a holding voltage similar to that of the 1-finger device.

RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process

In order to meet the requirement of ultrahigh-speed, low latency, and wide bandwidth (BW) in the next 5G mobile network and internet of things (IoT) applications, the parasitic capacitance specification of electrostatic discharge (ESD) protection devices should become much stricter. Reducing the capacitance always degrades the ESD performance in terms of shrinking the size of the ESD protection device. The distributed ESD protection network is one of the solutions which mitigates the capacitance issue and provides a broadband design. However, while the ESD devices are put under the I/O pad in the distributed ESD protection network, back-end-of-line (BEOL) capacitance starts to play an important role in the advanced 28-nm CMOS process. Therefore, a tapered metal structure is proposed to significantly reduce 30% BEOL capacitance of the ESD device, which can gain a 2.8-GHz increase in the operational BW in the distributed network. Meanwhile, it can enhance the human-body-model (HBM) level up to 16% higher than the original layout style under the same front-end-of-line (FEOL) layout size.

Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High- Speed Digital Application in 16-nm FinFET Process

The FinFET architecture has widely been used in the digital circuit application, due to the good short channel effect control and driving current boost. However, the worse thermal dispassion and smaller effective silicon volume would cause the significant impacts during the circuits under electrostatic discharge (ESD) event. Thus, the ESD protection device should be installed into the high-speed digital circuit to enhance the ESD robustness. To avoid the effect of circuit performance, the parasitic capacitance of ESD device must be as low as possible. In this article, two types of Fin-diode-triggered rotated silicon-controlled rectifier (SCR) with dual ESD current path have been proposed and verified in a 16-nm FinFET CMOS process. The proposed devices have better current-handling capability, sufficiently low parasitic, compact layout area, and low leakage current.

The impact of radiation and temperature effects on dual-direction SCR devices for on-chip ESD protections

The reliability issues of integrated circuits are attracting more attention, especially in extreme environments like radiation and elevated temperature conditions. The impact of ionizing radiation and temperature effects on the electrostatic discharge (ESD) protection devices should not be negligible. In this paper, A low-voltage dual-direction silicon controlled rectifier (DDSCR) and a high-voltage DDSCR based on laterally diffused metal oxide semiconductor are chosen and fabricated in a 5 V/18 V Bipolar-CMOS-DMOS process. To study the combined effects of ESD and total-ionizing dose, transmission line pulse (TLP) measurements are conducted right after exposure to 60Co gamma-ray up to 200 krad(Si). Besides, the TLP tests are performed at different temperatures ranging from 300 to 400 K to show the impact of elevated temperature on ESD devices. In the meanwhile, the physical mechanisms of the synergistic effects are investigated by means of three-dimensional (3D) TCAD simulations.

An Improved Silicon-Controlled Rectifier (SCR) for Low-Voltage ESD Application

In this article, an improved silicon-controlled rectifier (SCR) for low-voltage (LV) electrostatic discharge (ESD) applications has been presented. By employing an N+/P-ESD diode and optimizing the SCR layout, both the triggering and current-discharging paths of the new SCR become much shorter than the prior arts, thus generating better clamping ability, faster turn-on speed, and lower overshoot voltage. As a result, the human body model (HBM) robustness increases by 19%, 46%, and 267% for the proposed device with one, two, and three stacking units, respectively, and the charged-device model (CDM) robustness and turn-on speed of the improved device increase by 80% and 27%, respectively, over its conventional counterpart. Furthermore, the contradiction between quasi-static triggering characteristics and transient overshoot voltage frequent in current-assisted triggering of ESD devices has been investigated, where the common method to optimize the trigger voltage by increasing the resistance of triggering path will deteriorate the overshoot characteristics hugely. To make the ESD devices satisfy the emerging higher CDM protection requirement, a tradeoff between the quasi-static trigger voltage and the transient overshoot voltage should be made elaborately.

3D TCAD Analysis Enabling ESD Layout Design Optimization

On-chip electrostatic discharge (ESD) protection design for integrated circuits (ICs) is a challenging design-for-reliability problem. Since ESD events involve very high current transients in very short time period, current crowding is unavoidable, which leads to local overheating and creates local hot spots, resulting in ESD thermal failures. Therefore, layout design plays a critical role in practical ESD protection designs, which cannot be addressed by 2D TCAD ESD simulation. This article reports a comprehensive ESD simulation analysis by comparing true 3D TCAD with 2D TCAD, using exemplar diode ESD devices in a 55nm CMOS, which reveals 3D ESD discharging behaviors upon ESD layout variations. It concludes that true 3D TCAD ESD simulation is a powerful technique to enable ESD layout design optimization in real-world ESD protection designs.

High-Voltage ESD Protection Device With Fast Transient Reaction and High Holding Voltage

A stacked p-n-p(s) and grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) solution, with higher holding voltage ( ${V}_{H}$ ) and faster transient reaction than a p-n-p-embedded SCR, is proposed for high-voltage (HV) applications. The lowering of the beta gain ( $\beta$ ) of the p-n-p by the use of a deep-N-well (DNW)-based p-n-p in the proposed ESD device is a key to weakening the parasitic SCR action and results in an increase of ${V}_{H}$ . A lower voltage overshoot and fast transient reaction in a charged device model (CDM) event are due to the ggNMOS (parasitic n-p-n). The trigger and ESD shunting mechanisms are determined by the p-n-p(s) in series with the ggNMOS. This is an attractive configuration for achieving an effective, HV ESD device with high ${V}_{H}$ and low-voltage overshoot under CDM conditions.

An Enhanced MLSCR Structure Suitable for ESD Protection in Advanced Epitaxial CMOS Technology

In this paper, an enhanced modified lateral silicon-controlled rectifier (EMLSCR) has been proposed and demonstrated. Compared with the traditional MLSCR, the EMLSCR possesses a lower trigger voltage of 7.0 V as well as a higher robustness, making it very suitable for the electrostatic discharge (ESD) protection for 2.5-V/3.3-V/5-V IOs in the advanced 65-nm epitaxial CMOS technology. Additionally, an improved transmission line pulsing (TLP) measurement strategy by adopting TLP pulses with various rise time has been put forward to provide a convenient and economical approach to explore the conduction uniformity of the ESD device for the first time. Furthermore, two optimization methods are proposed and evaluated to overcome the prefailure issue due to the small well resistance inherited in the EPI process as well. The method of well pickup segmentation is demonstrated to be more efficient since it could increase the well resistance and augment the effective emitter area of parasitic bipolar junction transistors (BJTs) under constant device area.

A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models

Full-chip electrostatic discharge (ESD) protection circuit design verification is needed for complex ICs at advanced technology nodes despite being largely impractical due to the limitation of ESD device models and CAD tools. This paper reports a new circuit-level ESD protection design simulation and dynamic checking method using SPICE and ESD device behavior models which allows comprehensive, quantitative, and dynamic verification of ESD protection circuit designs at chip level-based entirely on ESD discharging functions. The new ESD protection circuit simulation method is validated using ICs designed and fabricated in a 28 nm CMOS. This ESD-function-based ESD circuit simulation method is technology independent, which can handle various ICs including complex multiple power domain circuits and ICs using nontraditional ESD protection structures.

Design and theoretical comparison of input ESD devices in 180 nm CMOS with focus on low capacitance

With the last decade’s advances in sensor technologies and packaging techniques, there are several applications where the input capacitance and the leakage current of the integrated circuit (IC) front-end limit the readout accuracy of sensor systems. In particular, optimization of the electrostatic discharge (ESD) protection devices at the IC input could improve performance. Specifically, such optimization should involve reduction of parasitic capacitance and leakage current while maintaining the ESD robustness. Several ESD devices have been analyzed against input capacitance, leakage current and robust ESD performance. The first device of interest is a diode, as the simplest solution and then there are three MOS transistor based devices, gate-grounded NMOS (GGNMOS), gate-coupled NMOS (GCNMOS), and substrate pump NMOS (SPNMOS). The target fabrication process is 180 nm CMOS. Theoretical analysis of capacitance simulated with Cadence® in 180 nm CMOS design kit including layout extracted parasitics in combination with TCAD Sentaurus® simulations of current density and temperature is presented for selected ESD devices.