Abstract
On-chip electrostatic discharge (ESD) protection design for integrated circuits (ICs) is a challenging design-for-reliability problem. Since ESD events involve very high current transients in very short time period, current crowding is unavoidable, which leads to local overheating and creates local hot spots, resulting in ESD thermal failures. Therefore, layout design plays a critical role in practical ESD protection designs, which cannot be addressed by 2D TCAD ESD simulation. This article reports a comprehensive ESD simulation analysis by comparing true 3D TCAD with 2D TCAD, using exemplar diode ESD devices in a 55nm CMOS, which reveals 3D ESD discharging behaviors upon ESD layout variations. It concludes that true 3D TCAD ESD simulation is a powerful technique to enable ESD layout design optimization in real-world ESD protection designs.
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